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| author | peichao.wang <peichao.wang@bitland.corp-partner.google.com> | 2018-10-09 12:18:31 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-10-10 18:38:38 +0000 |
| commit | d5325ddcc27535e13a224cb62759933186de0d39 (patch) | |
| tree | 925ae6fa146ce56010b7d29a4e5a4a25ed4fd1c7 /src/soc/intel/skylake | |
| parent | 4b6f262eadeddfd1f333f7ce05b2a46a5f39b8bf (diff) | |
| download | coreboot-d5325ddcc27535e13a224cb62759933186de0d39.tar.gz coreboot-d5325ddcc27535e13a224cb62759933186de0d39.tar.bz2 coreboot-d5325ddcc27535e13a224cb62759933186de0d39.zip | |
mb/google/octopus: Drop I2C bus 0 clock frequency for Phaser
Need to tune I2C bus 0 clock frequency under the 400KHz
since this bus attached the Stylus EMR pen and need meet the spec.
Bug=b:117297214
TEST=flash coreboot to the DUT and measure I2C bus 0 clock
frequency whether under 400KHz
Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28973
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
0 files changed, 0 insertions, 0 deletions