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| author | Michael Niewöhner <foss@mniewoehner.de> | 2022-03-13 20:08:55 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-15 19:22:19 +0000 |
| commit | d3b85223fdac1f9197c645f81d624d6a1f47b0bb (patch) | |
| tree | 78aa3a8fbe5c569c0f191f0e52e756d162f813df /src/soc/intel/tigerlake/Kconfig | |
| parent | bba7e601a86bd0dc375239ccbf48d3a4b1b52ce4 (diff) | |
| download | coreboot-d3b85223fdac1f9197c645f81d624d6a1f47b0bb.tar.gz coreboot-d3b85223fdac1f9197c645f81d624d6a1f47b0bb.tar.bz2 coreboot-d3b85223fdac1f9197c645f81d624d6a1f47b0bb.zip | |
soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.
Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/Kconfig')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 6d201127d65b..2b673cab5c82 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -94,6 +94,9 @@ config MAX_CPUS default 16 if SOC_INTEL_TIGERLAKE_PCH_H default 8 +config DIMM_SPD_SIZE + default 512 + config DCACHE_RAM_BASE default 0xfef00000 |