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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-02 16:19:14 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-13 13:54:52 +0000 |
| commit | 1ac0dc164d81f28602668cdb559b44f18dd4227d (patch) | |
| tree | cd52a6330f2afb8343fbaa37857e3caa7113ed30 /src/soc/intel/tigerlake/Makefile.inc | |
| parent | dcf045918b8584d23e487f70959ebbb2ef4492b6 (diff) | |
| download | coreboot-1ac0dc164d81f28602668cdb559b44f18dd4227d.tar.gz coreboot-1ac0dc164d81f28602668cdb559b44f18dd4227d.tar.bz2 coreboot-1ac0dc164d81f28602668cdb559b44f18dd4227d.zip | |
soc/intel/tigerlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Tiger Lake.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/tigerlake/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 6da5e0071363..25a1d6541002 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += lockdown.c ramstage-y += lpm.c ramstage-y += me.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += soundwire.c |