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| author | Duncan Laurie <dlaurie@google.com> | 2020-04-29 12:40:08 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-05-22 01:48:39 +0000 |
| commit | 2d0655008fa85d19c0c9e95dec9b26522fe2951f (patch) | |
| tree | 041298056dae7ac2953b70ac720486234ab15cd6 /src/soc/intel/tigerlake/Makefile.inc | |
| parent | c2891f15fdc1a18220477485e2fe2f8a84a51bc2 (diff) | |
| download | coreboot-2d0655008fa85d19c0c9e95dec9b26522fe2951f.tar.gz coreboot-2d0655008fa85d19c0c9e95dec9b26522fe2951f.tar.bz2 coreboot-2d0655008fa85d19c0c9e95dec9b26522fe2951f.zip | |
soc/intel/tigerlake: Provide SoundWire controller properties
The Intel Tigerlake SoundWire controller has 4 master links which
are configured differently depending on the external crystal oscillator
which is connected to the PCH.
This function will read the PCH PMC EPOC register to determine the
frequency and then fill out the master link entries with the correct
table values.
The frequency is also provided directly in a custom "ip-clock" property
which will be added to the link descriptor and passed to the OS driver
so it can know the clock rate of the master.
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I98b7df21210c29cd8defeff648f2c2207d629295
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/tigerlake/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 51422f9c643b..9ff767cfecee 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -42,6 +42,7 @@ ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smmrelocate.c +ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += me.c |