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| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-03-23 10:13:10 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-01 19:12:30 +0000 |
| commit | 555c9b6268febf001e887fbb9e3c3f0901a371ac (patch) | |
| tree | d3b1968356086c05ac0894115f45b06cb8437e85 /src/soc/intel/tigerlake/Makefile.inc | |
| parent | a23e0c9d74b7f06738ebf28b068e1bd63f246982 (diff) | |
| download | coreboot-555c9b6268febf001e887fbb9e3c3f0901a371ac.tar.gz coreboot-555c9b6268febf001e887fbb9e3c3f0901a371ac.tar.bz2 coreboot-555c9b6268febf001e887fbb9e3c3f0901a371ac.zip | |
soc/intel/tigerlake: Remove Jasper Lake SoC references
This implementation removes all JSL references from the TGL SoC code.
Additionally, mainboard code changes are done to support build.
BUG=b:150217037
TEST=build tglrvp and volteer
Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/tigerlake/Makefile.inc | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 12d59b1f9387..fd2464d50593 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -20,15 +20,12 @@ bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c -bootblock-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c -bootblock-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +bootblock-y += gpio.c bootblock-y += p2sb.c romstage-y += espi.c -romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c -romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += meminit_jsl.c -romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c -romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +romstage-y += meminit.c +romstage-y += gpio.c romstage-y += reset.c ramstage-y += acpi.c @@ -37,10 +34,8 @@ ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c -ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c -ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c -ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c -ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c @@ -50,15 +45,14 @@ ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c -smm-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c -smm-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +smm-y += gpio.c smm-y += p2sb.c smm-y += pmc.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c -verstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c +verstage-y += gpio.c CPPFLAGS_common += -I$(src)/soc/intel/tigerlake CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include |