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| author | Dinesh Gehlot <digehlot@google.com> | 2023-02-20 13:25:20 +0000 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-02-24 11:56:17 +0000 |
| commit | f9919574f4f6afb69e39aa6aca39856bdbcf9900 (patch) | |
| tree | 42a8e756935939d11e2fbcd9b14661cbc84abf1d /src/soc/intel/tigerlake/Makefile.inc | |
| parent | ef2e4fcb70c45cf423d2024e5e5f57df69e2d02b (diff) | |
| download | coreboot-f9919574f4f6afb69e39aa6aca39856bdbcf9900.tar.gz coreboot-f9919574f4f6afb69e39aa6aca39856bdbcf9900.tar.bz2 coreboot-f9919574f4f6afb69e39aa6aca39856bdbcf9900.zip | |
soc/intel/tgl: Select CSE defined ME spec version for tigerlake
Tigerlake based SoCs uses Intel's Management Engine (ME), version 15.
This patch selects ME 15 specification defined at common code and
removes tigerlake SoC specific ME code and data structures.
BUG=b:260309647
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: If4fbfd7c591794ed945c1e9e8487a9e9723c7551
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73138
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/tigerlake/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index e8cd7b32b885..435572e10aaf 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -32,7 +32,6 @@ ramstage-y += fsp_params.c ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += lpm.c -ramstage-y += me.c ramstage-y += p2sb.c ramstage-y += pcie_rp.c ramstage-y += pmc.c |