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| author | John Zhao <john.zhao@intel.com> | 2020-05-26 21:19:19 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-12 19:29:59 +0000 |
| commit | 6aedba2f134b8154a342248deae49bc37fc234ce (patch) | |
| tree | c4680040460f004f6df28ee245cd005afccffa35 /src/soc/intel/tigerlake/acpi | |
| parent | 21aece86533093ec01a64be42fcb0fe23d5281b8 (diff) | |
| download | coreboot-6aedba2f134b8154a342248deae49bc37fc234ce.tar.gz coreboot-6aedba2f134b8154a342248deae49bc37fc234ce.tar.bz2 coreboot-6aedba2f134b8154a342248deae49bc37fc234ce.zip | |
soc/intel/tigerlake: Configure Type-C Input Output Manager(IOM) device
This adds Type-C Intel Input Output Manager(IOM) device with HID
INTC1072. It provides MMIO range from 0xfbc10000 with size 0x1600.
Intel Input Output Manager(IOM) kernel driver reads relevant
information such as Type-C port status (whether a device is connected
to a Type-C port or not) and the activity type on the Type-C ports
(such as USB, Display Port, Thunderbolt) using this memory resource.
BUG=b:156016218
TEST=Able to detect USB, TBT and USB4 on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic733e831643bda6e052edf797ba0e6206eb4ddd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41762
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/acpi')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss.asl | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 3312b597b56b..33c1107a05dd 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -318,6 +318,16 @@ Scope (_GPE) Scope (\_SB.PCI0) { + Device (IOM) + { + Name (_HID, "INTC1072") + Name (_DDN, "Intel(R) Tiger Lake Input Output Manager(IOM) driver") + /* IOM preserved MMIO range from 0xFBC10000 to 0xFBC11600. */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) + }) + } + /* * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR. |