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| author | Michael Niewöhner <foss@mniewoehner.de> | 2022-01-08 20:47:11 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:29:38 +0000 |
| commit | 45b6080561748fe579c8ee901811cf4043383c2f (patch) | |
| tree | b9f37ad3e3962571401fafa2578788f0feb27d5a /src/soc/intel/tigerlake/fsp_params.c | |
| parent | 9f0285b6fe46d6ec76faad0c099239c227e5caa1 (diff) | |
| download | coreboot-45b6080561748fe579c8ee901811cf4043383c2f.tar.gz coreboot-45b6080561748fe579c8ee901811cf4043383c2f.tar.bz2 coreboot-45b6080561748fe579c8ee901811cf4043383c2f.zip | |
soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index f04c3d7b5a1d..1cf3d2fee890 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -402,6 +402,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->PcieRpAdvancedErrorReporting[i]; params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; params->PciePtm[i] = config->PciePtm[i]; + params->PcieRpSlotImplemented[i] = config->PcieRpSlotImplemented[i]; } /* Enable ClkReqDetect for enabled port */ |