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| author | Nick Vaccaro <nvaccaro@google.com> | 2021-05-11 16:39:32 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-05-14 23:00:01 +0000 |
| commit | 4b3e06edf2b7c2d99912038589764d551bc00c6f (patch) | |
| tree | 3a04517ed77edd47084e6707582978c0ab193c32 /src/soc/intel/tigerlake/fsp_params.c | |
| parent | 1b242b6618d4cbb80d5b4268ba2b39ae363d96f9 (diff) | |
| download | coreboot-4b3e06edf2b7c2d99912038589764d551bc00c6f.tar.gz coreboot-4b3e06edf2b7c2d99912038589764d551bc00c6f.tar.bz2 coreboot-4b3e06edf2b7c2d99912038589764d551bc00c6f.zip | |
soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC
We need to change OC pin for type C USB3 ports and it depends
on the board design. Allowing it to be filled by devicetree will
make it easier to change the mapping based on the board design.
BUG=b:184660529
TEST="emerge-volteer coreboot" compiles without error.
Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 1f1f3652f067..7c9ab88ec285 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -269,6 +269,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, sizeof(config->PcieRpClkReqDetect)); + for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { + if (config->tcss_ports[i].enable) + params->CpuUsb3OverCurrentPin[i] = + config->tcss_ports[i].ocpin; + } + /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { |