diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-22 10:43:42 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-06 04:12:59 +0000 |
| commit | 59a621abc70464352eaf540bd6cb896935b9ba72 (patch) | |
| tree | fec081238c01e28e0d31733444ed7ec7d7695a61 /src/soc/intel/tigerlake/fsp_params.c | |
| parent | 6dc72022a5b8cfb0299e741b86d26b6a208838f1 (diff) | |
| download | coreboot-59a621abc70464352eaf540bd6cb896935b9ba72.tar.gz coreboot-59a621abc70464352eaf540bd6cb896935b9ba72.tar.bz2 coreboot-59a621abc70464352eaf540bd6cb896935b9ba72.zip | |
soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
TGL boards using the Type-C subsystem for USB Type-C ports without a
retimer attached may require a DC bias on the aux lines for certain
modes to work. This patch adds native coreboot support for programming
the IOM to handle this DC bias via a simple devicetree
setting. Previously a UPD was required to tell the FSP which GPIOs were
used for the pullup and pulldown biases, but the API for this UPD was
effectively undocumented.
BUG=b:174116646
TEST=Verified on volteer2 that a Type-C flash drive is enumerated
succesfully on all ports. Verified all major power flows (boot, reboot,
powerdown and S0ix/suspend) still work as expected.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 9fbf9bd009ef..1f1f3652f067 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -23,6 +23,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <soc/tcss.h> #include <string.h> /* THC assignment definition */ @@ -188,8 +189,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; - for (i = 0; i < 8; i++) - params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; + + /* Explicitly clear this field to avoid using defaults */ + memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg)); /* * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will @@ -460,8 +462,10 @@ void platform_fsp_multi_phase_init_cb(uint32_t phase_index) printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", __FILE__, __func__); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) - tcss_configure(); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { + const config_t *config = config_of_soc(); + tcss_configure(config->typec_aux_bias_pads); + } break; default: break; |