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| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2020-08-18 18:54:49 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-09-23 16:24:42 +0000 |
| commit | 5b7daa224cb035f87c3b71105bb453849c7d54d4 (patch) | |
| tree | 8c788d990f3a6c93be8c486cfdaa085eead8d2a1 /src/soc/intel/tigerlake/fsp_params.c | |
| parent | 81ab88b416caafc8a23b532e54dc4c1d0597f6af (diff) | |
| download | coreboot-5b7daa224cb035f87c3b71105bb453849c7d54d4.tar.gz coreboot-5b7daa224cb035f87c3b71105bb453849c7d54d4.tar.bz2 coreboot-5b7daa224cb035f87c3b71105bb453849c7d54d4.zip | |
soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widths
Configure FSP UPDs for the chipset minimum assertion widths and
power cycle duration per mainboard variants.
* PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
* PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
* PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
* PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
* PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
* Check to avoid violating the PCH EDS recommendation for the
PchPmPwrCycDur setting.
BUG=b:159108661
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44557
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 73a620d46586..1c5490b0f8e3 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -10,6 +10,7 @@ #include <intelblocks/cse.h> #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> +#include <intelblocks/pmclib.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <security/vboot/vboot_common.h> @@ -331,6 +332,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } + /* Apply minimum assertion width settings if non-zero */ + if (config->PchPmSlpS3MinAssert) + params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; + if (config->PchPmSlpS4MinAssert) + params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert; + if (config->PchPmSlpSusMinAssert) + params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert; + if (config->PchPmSlpAMinAssert) + params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert; + + /* Set Power Cycle Duration */ + if (config->PchPmPwrCycDur) + params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert, + config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, + config->PchPmPwrCycDur); + /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ params->EnableMultiPhaseSiliconInit = 1; mainboard_silicon_init_params(params); |