diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-07 13:40:19 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-01-19 09:57:47 +0000 |
| commit | 56ab8e2aae25efc839daeb56d5922e66d2680aec (patch) | |
| tree | 2790032028d9ddba711fe08a3eaab3105d571acd /src/soc/intel/tigerlake/include/soc/msr.h | |
| parent | 6ac5dc2ca6a6b09d1b0156c2db6aa1385ccaf13e (diff) | |
| download | coreboot-56ab8e2aae25efc839daeb56d5922e66d2680aec.tar.gz coreboot-56ab8e2aae25efc839daeb56d5922e66d2680aec.tar.bz2 coreboot-56ab8e2aae25efc839daeb56d5922e66d2680aec.zip | |
soc/intel/common/cpu: Use SoC overrides to get CPU privilege level
This patch implements a SoC overrides to check CPU privilege level
as the MSR is not consistent across platforms.
For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR
0x151.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/tigerlake/include/soc/msr.h')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/msr.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/msr.h b/src/soc/intel/tigerlake/include/soc/msr.h index 954fce0a8259..5bdbf92e8b61 100644 --- a/src/soc/intel/tigerlake/include/soc/msr.h +++ b/src/soc/intel/tigerlake/include/soc/msr.h @@ -5,6 +5,8 @@ #include <intelblocks/msr.h> -#define MSR_VR_MISC_CONFIG2 0x636 +#define MSR_BIOS_DONE 0x151 +#define ENABLE_IA_UNTRUSTED (1 << 0) +#define MSR_VR_MISC_CONFIG2 0x636 #endif |