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author | Nick Vaccaro <nvaccaro@google.com> | 2020-08-05 14:45:58 -0700 |
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committer | Nick Vaccaro <nvaccaro@google.com> | 2020-08-06 17:42:20 +0000 |
commit | 0cc63ccaa26c21d02025f3b1c31f2fc4e8adc697 (patch) | |
tree | 83d0323ea9239f07bba1701192fdaa8d15bcf60d /src/soc/intel/tigerlake/meminit.c | |
parent | 7245a098d0c012aa2c1e9152080f0bda1e3bce03 (diff) | |
download | coreboot-0cc63ccaa26c21d02025f3b1c31f2fc4e8adc697.tar.gz coreboot-0cc63ccaa26c21d02025f3b1c31f2fc4e8adc697.tar.bz2 coreboot-0cc63ccaa26c21d02025f3b1c31f2fc4e8adc697.zip |
soc/intel/tigerlake: add common routine for DDR init
Add a common routine meminit_ddr() that calls the appropriate meminit
routine based on whether the memory type requested is LPDDR4x or DDR4.
BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that
volteer still boots. NOTE that this only tests the lpddr4 side
of the implementation. I do not have a DDR4 board to test this on.
Change-Id: Ib2039eb89211efc48d10897eb679d05f567ae5a1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/meminit.c')
-rw-r--r-- | src/soc/intel/tigerlake/meminit.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 790e2e049967..0c6f0b0f8862 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -435,3 +435,20 @@ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, } } } + +void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, + const struct spd_info *info, bool half_populated) +{ + switch (board_cfg->mem_type) { + case MEMTYPE_DDR4: + meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, + half_populated); + break; + case MEMTYPE_LPDDR4X: + meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, + half_populated); + break; + default: + die("Unsupported memory type = %d!\n", board_cfg->mem_type); + } +} |