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| author | Sean Rhodes <sean@starlabs.systems> | 2023-02-06 09:23:47 +0000 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-02-20 10:14:49 +0000 |
| commit | 6bfca1b689e48be4f72e8fa401f3558d845fc282 (patch) | |
| tree | 6b1ee5296f341e08a0f815fd4f4f9fe3b027b132 /src/soc/intel/tigerlake | |
| parent | dbb97c3243e55a0fd00e692d150c9d38d09b57af (diff) | |
| download | coreboot-6bfca1b689e48be4f72e8fa401f3558d845fc282.tar.gz coreboot-6bfca1b689e48be4f72e8fa401f3558d845fc282.tar.bz2 coreboot-6bfca1b689e48be4f72e8fa401f3558d845fc282.zip | |
soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive`
so their configurations are unchanged.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index b823f503015f..a10db87202de 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -323,11 +323,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* D3Hot and D3Cold for TCSS */ params->D3HotEnable = !config->TcssD3HotDisable; + cpu_id = cpu_get_cpuid(); if (cpu_id == CPUID_TIGERLAKE_A0) params->D3ColdEnable = 0; else - params->D3ColdEnable = !config->TcssD3ColdDisable; + params->D3ColdEnable = CONFIG(D3COLD_SUPPORT); params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; |