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| author | Michael Niewöhner <foss@mniewoehner.de> | 2022-01-09 02:14:38 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-12 16:09:20 +0000 |
| commit | a421b1a289fd173da609a4d1e2625c44ad1faad4 (patch) | |
| tree | b7678f69b727bf5c9b2bee1741265b83b06de070 /src/soc/intel/tigerlake | |
| parent | a52b9c3a40dd082213b419f62d6ae3e1e071363b (diff) | |
| download | coreboot-a421b1a289fd173da609a4d1e2625c44ad1faad4.tar.gz coreboot-a421b1a289fd173da609a4d1e2625c44ad1faad4.tar.bz2 coreboot-a421b1a289fd173da609a4d1e2625c44ad1faad4.zip | |
soc/intel/tgl/pcie_rp: correct root port map
TGL-LP only has 12 root ports, not 20. Correct the port map.
Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/pcie_rp.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c index ceb85d8aede6..5966af6c2b03 100644 --- a/src/soc/intel/tigerlake/pcie_rp.c +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -8,8 +8,7 @@ static const struct pcie_rp_group pch_lp_rp_groups[] = { { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_2, .count = 4 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, { 0 } }; |