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| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-05-20 11:55:36 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:11:03 +0000 |
| commit | b30fe36734df3c48ec35438052ee8b28bf7a6a44 (patch) | |
| tree | 3292f94f475a09678df0fc56f5450e6388c1fa2c /src/soc/intel/tigerlake | |
| parent | b4d7116a740b2847ef112cc1954462dac0b4cf85 (diff) | |
| download | coreboot-b30fe36734df3c48ec35438052ee8b28bf7a6a44.tar.gz coreboot-b30fe36734df3c48ec35438052ee8b28bf7a6a44.tar.bz2 coreboot-b30fe36734df3c48ec35438052ee8b28bf7a6a44.zip | |
soc/intel/tigerlake: Remove MIPI clock setting from devicetree
In Tiger Lake we have support for enabling MIPI clocks at runtime in
ACPI. Hence remove setting pch_islclk from devcietree and chip.h.
Also update functions which reference pch_isclk.
BUG=b:148884060
Branch=None
Test=build and boot volteer and verify camera functionality
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/finalize.c | 20 |
2 files changed, 0 insertions, 23 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 86e703b05598..5892829ef4d1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -206,9 +206,6 @@ struct soc_intel_tigerlake_config { DEBUG_INTERFACE_TRACEHUB = (1 << 5), } debug_interface_flag; - /* Enable Pch iSCLK */ - uint8_t pch_isclk; - /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ enum { FORCE_DISABLE, diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 7de64a3a5036..a402625799ce 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -27,24 +27,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> -#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ -#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ -#define CAM_CLK_EN (1 << 1) -#define MIPI_CLK (1 << 0) -#define HDPLL_CLK (0 << 0) - -static void pch_enable_isclk(void) -{ - pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); - pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); -} - -static void pch_handle_sideband(config_t *config) -{ - if (config->pch_isclk) - pch_enable_isclk(); -} - static void pch_finalize(void) { uint32_t reg32; @@ -83,8 +65,6 @@ static void pch_finalize(void) write32(pmcbase + CPPMVRIC, reg32); } - pch_handle_sideband(config); - pmc_clear_pmcon_sts(); } |