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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-01-26 00:28:10 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-06 17:34:11 +0000 |
| commit | fad76f33a9be2b629266f4f4276345970a1b6ebd (patch) | |
| tree | effd5d85793a5771cd2e6f51b3630b2d023c716d /src/soc/intel/tigerlake | |
| parent | f5e94b6e7283794bad7a0c527c6c75dc92d6f460 (diff) | |
| download | coreboot-fad76f33a9be2b629266f4f4276345970a1b6ebd.tar.gz coreboot-fad76f33a9be2b629266f4f4276345970a1b6ebd.tar.bz2 coreboot-fad76f33a9be2b629266f4f4276345970a1b6ebd.zip | |
mb/google/brya: Enable dynamic debug capability for brya family
The patch enables dynamic debug capability for Brya family of boards.
BRANCH=MAIN
BUG=b:153410586
TEST= Verified the CSE firmware update functionality on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
0 files changed, 0 insertions, 0 deletions