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| author | Marc Jones <marcjones@sysproconsulting.com> | 2020-10-19 21:12:27 -0600 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2020-10-30 18:55:42 +0000 |
| commit | 444fda45287822920d389809d9dd1f935f22c592 (patch) | |
| tree | 509c51f661b80a06f97f57b9fd515cc6dd9be7ad /src/soc/intel/xeon_sp/cpx/Makefile.inc | |
| parent | d49c8cfbf132aace89db372fad86116cd20a9acd (diff) | |
| download | coreboot-444fda45287822920d389809d9dd1f935f22c592.tar.gz coreboot-444fda45287822920d389809d9dd1f935f22c592.tar.bz2 coreboot-444fda45287822920d389809d9dd1f935f22c592.zip | |
soc/intel/xeon_xp: Combine cpx and skx acpi.c
Prepare for common ACPI. Combine cpx and skx acpi.c into a single
file in xeon_sp. This is almost the last step in using common/block
acpi.
Change-Id: I5f40eb7909bb796907682c548219c7515f2ae4d1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46600
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/Makefile.inc')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 79a83b541672..b2e653e50e96 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -12,7 +12,7 @@ romstage-y += romstage.c ddr.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -ramstage-y += chip.c acpi.c cpu.c soc_util.c ramstage.c soc_acpi.c +ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c |