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| author | Jonathan Zhang <jonzhang@fb.com> | 2020-04-02 20:03:48 -0700 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2020-06-06 07:44:07 +0000 |
| commit | b7cf7d36d7cf97b0cce437b9f1577ca39eeb312d (patch) | |
| tree | d1df2f10fbaf6a582db3c9a8cbd2da5f14f7e09e /src/soc/intel/xeon_sp/cpx/Makefile.inc | |
| parent | eaa219b5bba95cfdc03b9b20d1c06d84bd33c702 (diff) | |
| download | coreboot-b7cf7d36d7cf97b0cce437b9f1577ca39eeb312d.tar.gz coreboot-b7cf7d36d7cf97b0cce437b9f1577ca39eeb312d.tar.bz2 coreboot-b7cf7d36d7cf97b0cce437b9f1577ca39eeb312d.zip | |
soc/intel/xeon_sp/cpx: set up cpus
Set up cpus:
* setup apic IDs.
* setup MSR to enable fast string, speed step, etc.
* Enable turbo
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I5765e98151f6ceebaabccc06db63d5911caf7ce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/Makefile.inc')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 54004a5be7a2..aca8572ed943 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) +subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc |