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| author | Tim Chu <Tim.Chu@quantatw.com> | 2020-12-28 00:08:53 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-09 06:16:42 +0000 |
| commit | 58e1e0aee938a5a539c35ae52bfe718e41f7b224 (patch) | |
| tree | bad3cbb1ae3d07607e1c837fc4c9ec5f5ef5697c /src/soc/intel/xeon_sp/cpx/chip.h | |
| parent | 5fa07217a4d3fa41fa93b7a05811584fad9dda7a (diff) | |
| download | coreboot-58e1e0aee938a5a539c35ae52bfe718e41f7b224.tar.gz coreboot-58e1e0aee938a5a539c35ae52bfe718e41f7b224.tar.bz2 coreboot-58e1e0aee938a5a539c35ae52bfe718e41f7b224.zip | |
mb/ocp/deltalake: Override DDR frequency limit via VPD variable
Use VPD variable "fsp_dimm_freq" to select DDR frequency limit.
Tested=On OCP Delta Lake, DDR frequency limit can be changed via VPD.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I1232feae5090420d8fa42596b46f2d4dcaf9d635
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/chip.h')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index 1311678116f5..abd358efabf8 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -31,6 +31,21 @@ typedef enum { PcieGen3 } pcie_link_speed; +/** + enum for DDR Frequency Limit + **/ +enum ddr_freq_limit { + DDR_AUTO = 0x0, + DDR_1333 = 0x5, + DDR_1600 = 0x7, + DDR_1866 = 0x9, + DDR_2133 = 0xb, + DDR_2400 = 0xd, + DDR_2666 = 0xf, + DDR_2933 = 0x11, + DDR_3200 = 0x13 +}; + struct soc_intel_xeon_sp_cpx_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; |