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| author | Tim Chu <Tim.Chu@quantatw.com> | 2022-11-25 10:31:00 +0000 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-12-22 19:05:13 +0000 |
| commit | 13c44457f1392d3074b126d9c29a722ea130db8c (patch) | |
| tree | 1adc94f99793b5e380524d717a11299b964025ca /src/soc/intel/xeon_sp/include/soc/pcr_ids.h | |
| parent | cfad59a5165209e8a5e12e6b66363f521472e48d (diff) | |
| download | coreboot-13c44457f1392d3074b126d9c29a722ea130db8c.tar.gz coreboot-13c44457f1392d3074b126d9c29a722ea130db8c.tar.bz2 coreboot-13c44457f1392d3074b126d9c29a722ea130db8c.zip | |
soc/intel/xeon_sp: Move codes to support new PCH
Different PCHs have different definitions for registers. Here create
a lbg folder and move lbg specific codes to this folder so that we
can add new PCH code under xeon_sp folder.
* Create lbg folder and move lbg specific codes from pch.c to soc_pch.c
under lbg folder.
* Rename lewisburg_pch_gpio_defs.h to gpio_soc_defs.h and move to lbg
folder.
* Rename gpio.c to soc_gpio.c and move to lbg folder.
* Move pcr_ids.h to lbg folder.
* Move lbg specific codes from pmutil.c to soc_pmutil.c under lbg
folder.
* Create and revise makefile for files under lbg folder.
TEST=Can boot into OS on OCP Delta Lake.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I06555ed6612c632ea2ce1938d81781cd9348017a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include/soc/pcr_ids.h')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pcr_ids.h | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h deleted file mode 100644 index 8c0b66945c68..000000000000 --- a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _PCR_IDS_H_ -#define _PCR_IDS_H_ - -#define PID_CSME0 0x90 -#define PID_ITSS 0xC4 -#define PID_RTC 0xC3 -#define PID_DMI 0xEF -#define PID_GPIOCOM5 0x11 -#define PID_GPIOCOM4 0xAB -#define PID_GPIOCOM3 0xAC -#define PID_GPIOCOM2 0xAD -#define PID_GPIOCOM1 0xAE -#define PID_GPIOCOM0 0xAF - -#endif /* _PCR_IDS_H_ */ |