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author | Jonathan Zhang <jonzhang@meta.com> | 2023-01-24 11:18:15 -0800 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-09 21:40:23 +0000 |
commit | 665d870244a26e28e445ac8e6945ddf986d9050a (patch) | |
tree | 07cea0977cce4d6b17ac607ab174c9211666618c /src/soc/intel/xeon_sp/include | |
parent | ca520a726a6d47c31c5a8c278e2a272b1f89bac4 (diff) | |
download | coreboot-665d870244a26e28e445ac8e6945ddf986d9050a.tar.gz coreboot-665d870244a26e28e445ac8e6945ddf986d9050a.tar.bz2 coreboot-665d870244a26e28e445ac8e6945ddf986d9050a.zip |
soc/intel/xeon_sp: rework lock_pam0123() to accomodate hidden SAD device
For Intel SPR-SP, the SAD device is hidden, so pcidev_path_on_bus()
returns NULL. Therefore use pci_s_write_config32() instead.
Move lock_pam0123() from finalize.c to util.c, to be together with
unlock_pam_regions().
Change-Id: Ib08d423d8c4d482612077b66dab3878018da8f2b
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
-rw-r--r-- | src/soc/intel/xeon_sp/include/soc/util.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index c794ac5b9d18..52afc48704f3 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -6,7 +6,9 @@ #include <cpu/x86/msr.h> #include <hob_iiouds.h> +void lock_pam0123(void); void unlock_pam_regions(void); + msr_t read_msr_ppin(void); int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); |