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| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-17 13:36:58 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-21 09:18:09 +0000 |
| commit | b48e6357e823dd6b01c9a0c9122079489ce8f190 (patch) | |
| tree | de382c137d807dca5d6193a4148e42597b9b97f4 /src/soc/intel/xeon_sp/include | |
| parent | 6a2ece7bd11d5ab2015af6ae01f119c1b532ca19 (diff) | |
| download | coreboot-b48e6357e823dd6b01c9a0c9122079489ce8f190.tar.gz coreboot-b48e6357e823dd6b01c9a0c9122079489ce8f190.tar.bz2 coreboot-b48e6357e823dd6b01c9a0c9122079489ce8f190.zip | |
soc/intel/xeon_sp: Drop unused functions and prototypes
No definition exists for pmc_set_disb() and rtc_failure() is not called.
Change-Id: I3a68e1fc55c62193735a46caf9f70dd9ee0b7349
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pm.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index 8c26c6ace34c..b4d6df987e4b 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -117,12 +117,6 @@ struct chipset_power_state { /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void); -/* Set the DISB after DRAM init */ -void pmc_set_disb(void); - -/* Return non-zero when RTC failure happened. */ -int rtc_failure(void); - uint16_t get_pmbase(void); void pmc_lock_smi(void); |