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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-15 16:42:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-23 06:32:21 +0000 |
| commit | bf46ba5adbd7cec13986d8b6584a2a14bfc9109e (patch) | |
| tree | d9bfc58519625a71f03f14858b56c814ec22dde0 /src/soc/intel/xeon_sp/include | |
| parent | 9abeb9c0626244e5f889536bbc9de0bf685eb922 (diff) | |
| download | coreboot-bf46ba5adbd7cec13986d8b6584a2a14bfc9109e.tar.gz coreboot-bf46ba5adbd7cec13986d8b6584a2a14bfc9109e.tar.bz2 coreboot-bf46ba5adbd7cec13986d8b6584a2a14bfc9109e.zip | |
soc/intel/xeon_sp: correct wrong gpio register base offsets
Reference: Intel doc# 633935-005 and 547817 rev1.5.
Change-Id: I38c20288a9839f8c3cf895f7b49941387bdca5e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Lance Zhao
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h b/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h index 2ad5fba38b5b..2049c3fcaf42 100644 --- a/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h +++ b/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h @@ -656,12 +656,12 @@ #define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 #define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 -#define HOSTSW_OWN_REG_0 0xd0 +#define HOSTSW_OWN_REG_0 0x80 #define PAD_CFG_BASE 0x400 #define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x120 -#define GPI_SMI_STS_0 0x180 -#define GPI_SMI_EN_0 0x1a0 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x140 +#define GPI_SMI_EN_0 0x150 #define GPI_NMI_STS_0 0x160 #define GPI_NMI_EN_0 0x170 |