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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-10-22 14:13:14 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-05 00:02:07 +0000 |
| commit | 1410224cf476ed5e666deffcbbc455055632add1 (patch) | |
| tree | 23f3df4f4588eb9de5efd8fb74289e1e62667724 /src/soc/intel/xeon_sp/memmap.c | |
| parent | 6c49f40b6e6342b7acb47cb0a57fa10269e3d4c9 (diff) | |
| download | coreboot-1410224cf476ed5e666deffcbbc455055632add1.tar.gz coreboot-1410224cf476ed5e666deffcbbc455055632add1.tar.bz2 coreboot-1410224cf476ed5e666deffcbbc455055632add1.zip | |
soc/intel/xeon_sp: Use common cpu/intel romstage entry
This removes some boilerplate like starting the console and also adds
a "start of romstage" timestamp.
Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/memmap.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/memmap.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index 79ab47eaedf0..edc62cf881fa 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> #include <device/pci_ops.h> #include <cpu/x86/smm.h> #include <soc/pci_devs.h> @@ -20,3 +23,21 @@ void smm_region(uintptr_t *start, size_t *size) *start = tseg_base; *size = tseg_limit - tseg_base; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16 * MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16 * MiB, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + if (CONFIG(TSEG_STAGE_CACHE)) + postcar_enable_tseg_cache(pcf); +} |