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| author | Michael Niewöhner <foss@mniewoehner.de> | 2023-04-07 17:05:49 +0000 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2023-04-12 15:19:56 +0000 |
| commit | 076f86125f5578b0cc58fa219f80a5a39af31b99 (patch) | |
| tree | e3c45d9f751a693f1e7e5a4e24d75dc84230fcfa /src/soc/intel | |
| parent | 7c722ce1795e58b3b5b3feb3053b850587e748d1 (diff) | |
| download | coreboot-076f86125f5578b0cc58fa219f80a5a39af31b99.tar.gz coreboot-076f86125f5578b0cc58fa219f80a5a39af31b99.tar.bz2 coreboot-076f86125f5578b0cc58fa219f80a5a39af31b99.zip | |
Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"
This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282.
Reason for revert: dependency for revert CB:73903
Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 3 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 704f910a697d..9b360e7b5af2 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -648,7 +648,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, /* D3Hot and D3Cold for TCSS */ s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; - s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT) && !config->tcss_d3_cold_disable; + s_cfg->D3ColdEnable = !CONFIG(SOC_INTEL_ALDERLAKE_S3) && !config->tcss_d3_cold_disable; s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index a10db87202de..b823f503015f 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -323,12 +323,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* D3Hot and D3Cold for TCSS */ params->D3HotEnable = !config->TcssD3HotDisable; - cpu_id = cpu_get_cpuid(); if (cpu_id == CPUID_TIGERLAKE_A0) params->D3ColdEnable = 0; else - params->D3ColdEnable = CONFIG(D3COLD_SUPPORT); + params->D3ColdEnable = !config->TcssD3ColdDisable; params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; |