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| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-23 15:50:13 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2022-08-14 10:53:47 +0000 |
| commit | 29e71b1291bd22366d75b4dc3c897b355ff268ce (patch) | |
| tree | 21fe08ac0057cdbf839b0f8a2f9d440e834c6900 /src/soc/intel | |
| parent | 2a90e396fc1b0d008024cff1a1b02ee8f1cd0036 (diff) | |
| download | coreboot-29e71b1291bd22366d75b4dc3c897b355ff268ce.tar.gz coreboot-29e71b1291bd22366d75b4dc3c897b355ff268ce.tar.bz2 coreboot-29e71b1291bd22366d75b4dc3c897b355ff268ce.zip | |
broadwell: Move some MRC/refcode settings to devicetree
There's no generic way to tell whether a mainboard has an EC or not.
Making Kconfig symbols for these options seems overkill, too. So, just
put them on the devicetree. Also, drop unnecessary assignments when the
board's current value is zero, as the struct defaults to zero already.
Change-Id: I8d3b352333bea7ea6f7b0f96d73e6c2d7d1a2cfb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55809
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/broadwell/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pei_data.c | 6 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 8d7225316280..2b5cccd56e44 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -21,6 +21,10 @@ struct soc_intel_broadwell_config { /* IGD panel configuration */ struct i915_gpu_panel_config panel_cfg; + bool ec_present; + + bool dq_pins_interleaved; + /* * Graphics CD Clock Frequency * 0 = 337.5MHz diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index db41b4bcc4ae..db33966c4c1b 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/streams.h> +#include <device/device.h> #include <soc/iomap.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> +#include <soc/intel/broadwell/chip.h> static void ABI_X86 send_to_console(unsigned char b) { @@ -12,6 +14,8 @@ static void ABI_X86 send_to_console(unsigned char b) void broadwell_fill_pei_data(struct pei_data *pei_data) { + const struct soc_intel_broadwell_config *cfg = config_of_soc(); + pei_data->pei_version = PEI_VERSION; pei_data->board_type = BOARD_TYPE_ULT; pei_data->usbdebug = CONFIG(USBDEBUG); @@ -24,6 +28,8 @@ void broadwell_fill_pei_data(struct pei_data *pei_data) pei_data->gpiobase = GPIO_BASE_ADDRESS; pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; pei_data->temp_mmio_base = 0xfed08000; + pei_data->ec_present = cfg->ec_present, + pei_data->dq_pins_interleaved = cfg->dq_pins_interleaved, pei_data->tx_byte = &send_to_console; pei_data->ddr_refresh_2x = 1; } |