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| author | Subrata Banik <subratabanik@google.com> | 2022-12-06 13:48:44 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-10 07:59:45 +0000 |
| commit | 3eac04982abb17dbd69e2303183cc2603df09630 (patch) | |
| tree | 58104de39a56b99255b75aea98097f1ac9d3940e /src/soc/intel | |
| parent | cb3291965d14dbd76880d359621183264a65c597 (diff) | |
| download | coreboot-3eac04982abb17dbd69e2303183cc2603df09630.tar.gz coreboot-3eac04982abb17dbd69e2303183cc2603df09630.tar.bz2 coreboot-3eac04982abb17dbd69e2303183cc2603df09630.zip | |
soc/intel/meteorlake: Check clkreq overlap
In some cases, partner may assign same clkreq on more than one devices.
This could happen when one device is in baseboard dev tree and another
one is in override dev tree.
This change adds a clkreq overlap check and shows a warning message.
This patch is backported from
commit ff553ba8b3d39fba6f1ed9b8e3513fc5412ba5a9 (soc/intel/alderlake:
Check clkreq overlap)
Change-Id: Ifc1c57578eca376685196ad497d9db825d63aa76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70414
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 7921f228e4b6..89f6aaf1919c 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -28,6 +28,7 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, const struct pcie_rp_config *cfg, size_t cfg_count) { size_t i; + static unsigned int clk_req_mapping = 0; for (i = 0; i < cfg_count; i++) { if (!(en_mask & BIT(i))) @@ -37,8 +38,13 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, /* flags 0 means, RP config is not specify from devicetree */ if (cfg[i].flags == 0) continue; - if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) + if (clk_req_mapping & (1 << cfg[i].clk_req)) + printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" + , cfg[i].clk_req); + if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; + clk_req_mapping |= 1 << cfg[i].clk_req; + } m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i; } } |