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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-06-30 11:07:28 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-07 15:52:19 +0000 |
| commit | 48827fdcef423881d72a1327f2d6f3659a6e7856 (patch) | |
| tree | c6cfddd7d9954be441b82c6511b6cf5bdcb82ad5 /src/soc/intel | |
| parent | 561780a54d00bd245b958dc2d0dce53e17f9e03f (diff) | |
| download | coreboot-48827fdcef423881d72a1327f2d6f3659a6e7856.tar.gz coreboot-48827fdcef423881d72a1327f2d6f3659a6e7856.tar.bz2 coreboot-48827fdcef423881d72a1327f2d6f3659a6e7856.zip | |
soc/intel/alderlake/acpi/gpio.asl: Add GPIO Commnity 3 for ADL-S
This patch fixes the issue with INTC1056 invalid resource reported by
alderlake-pinctrl Linux driver on ADL-S platform. The driver also
includes GPIO Community 3 in the GPIO list compared to ADL-N which
was missing in GPIO ACPI device.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A DDR4 WIFI and check there is
no invalid resource error reported by alderlake-pinctrl
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I23da68c247de86438cc2eef2b5a5a9aa711c1d7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/acpi/gpio.asl | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl index 8102d7a66171..702b07387b24 100644 --- a/src/soc/intel/alderlake/acpi/gpio.asl +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -16,6 +16,9 @@ Device (GPIO) { Memory32Fixed (ReadWrite, 0, 0, COM0) Memory32Fixed (ReadWrite, 0, 0, COM1) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + Memory32Fixed (ReadWrite, 0, 0, COM3) +#endif Memory32Fixed (ReadWrite, 0, 0, COM4) Memory32Fixed (ReadWrite, 0, 0, COM5) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) @@ -35,6 +38,14 @@ Device (GPIO) BAS1 = ^^PCRB (PID_GPIOCOM1) LEN1 = GPIO_BASE_SIZE +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE +#endif + /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) |