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| author | Kevin L Lee <kevin.l.lee@intel.com> | 2014-12-12 14:02:43 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 20:06:59 +0200 |
| commit | 5c8d43e207b4349e95ffb359e0ed08ffa3f789a0 (patch) | |
| tree | 1c6ab16fa1429d87cde744844f4613b917154677 /src/soc/intel | |
| parent | e6cf3c6f78149b4c11c7a53f27e684bd560c0ac2 (diff) | |
| download | coreboot-5c8d43e207b4349e95ffb359e0ed08ffa3f789a0.tar.gz coreboot-5c8d43e207b4349e95ffb359e0ed08ffa3f789a0.tar.bz2 coreboot-5c8d43e207b4349e95ffb359e0ed08ffa3f789a0.zip | |
baytrail: fix the coding error on PCIe L1 exit latency
The original code uses L1EXIT_MASK to shift the bit for
PCIe L1 exit latency, the code should use L1EXIT_SHIFT
for bit shifting.
BUG=chrome-os-partner:34037
BRANCH=None
TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15]
set to 010b. Correspond WIFI device performance got improvement.
Signed-off-by: Kevin L Lee <kevin.l.lee@intel.com>
Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be
Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92
Original-Reviewed-on: https://chromium-review.googlesource.com/234673
Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Tested-by: Kenji Chen <kenji.chen@intel.com>
Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: http://review.coreboot.org/9480
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/baytrail/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 187015801d28..e44ebc66dd9d 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -95,7 +95,7 @@ static void byt_pcie_init(device_t dev) /* Exit latency configuration based on * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, - 2 << (L1EXIT_MASK + pll_en_off)), + 2 << (L1EXIT_SHIFT + pll_en_off)), REG_SCRIPT_NEXT(init_static_after_exit_latency), /* Disable hot plug, set power to 10W, set slot number. */ REG_PCI_RMW32(SLCAP, ~(HPC | HPS), |