soc/intel: Expand SA_DEV_ROOT for ramstage

We do not want to disguise somewhat complex function
calls as simple macros.

Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

17 files changed, 68 insertions, 77 deletions

diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index c5eaf4c3e8fb..583cc5f70bfb 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -17,35 +17,32 @@
 
 #include <device/pci_def.h>
 
-#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot)		pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
 #define _PCH_DEV(slot, func)	pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
 #else
-#define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
 #endif
 
 /* System Agent Devices */
 
 #define SA_DEV_SLOT_ROOT	0x00
-#define  SA_DEVFN_ROOT		_SA_DEVFN(ROOT)
-#define  SA_DEV_ROOT		_SA_DEV(ROOT)
+#define  SA_DEVFN_ROOT		PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
+#define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
 
 #define SA_DEV_SLOT_PUNIT	0x01
-#define  SA_DEVFN_PUNIT		_SA_DEVFN(PUNIT)
-#define  SA_DEV_PUNIT		_SA_DEV(PUNIT)
+#define  SA_DEVFN_PUNIT		PCI_DEVFN(SA_DEV_SLOT_PUNIT, 0)
+#define  SA_DEV_PUNIT		PCI_DEV(0, SA_DEV_SLOT_PUNIT, 0)
 
 #define SA_DEV_SLOT_IGD		0x02
-#define  SA_DEVFN_IGD		_SA_DEVFN(IGD)
-#define  SA_DEV_IGD		_SA_DEV(IGD)
+#define  SA_DEVFN_IGD		PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
+#define  SA_DEV_IGD		PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
 
 #define SA_DEV_SLOT_IPU		0x03
-#define  SA_DEVFN_IPU		_SA_DEVFN(IPU)
-#define  SA_DEV_IPU		_SA_DEV(IPU)
+#define  SA_DEVFN_IPU		PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
+#define  SA_DEV_IPU		PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
 
 /* PCH Devices */
 
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index 1adbbc8aa220..06cc18d67a37 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -96,9 +96,11 @@ const struct reg_script pch_finalize_script[] = {
 
 static void broadwell_finalize(void *unused)
 {
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+
 	printk(BIOS_DEBUG, "Finalizing chipset.\n");
 
-	reg_script_run_on_dev(SA_DEV_ROOT, system_agent_finalize_script);
+	reg_script_run_on_dev(sa_dev, system_agent_finalize_script);
 	reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
 
 	/* Lock */
diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h
index ae3e08f6619d..7ab54141e5a5 100644
--- a/src/soc/intel/broadwell/include/soc/pci_devs.h
+++ b/src/soc/intel/broadwell/include/soc/pci_devs.h
@@ -16,32 +16,29 @@
 #ifndef _BROADWELL_PCI_DEVS_H_
 #define _BROADWELL_PCI_DEVS_H_
 
-#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
 
 #if defined(__SIMPLE_DEVICE__)
-#define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
 #else
 #include <device/device.h>
 #include <device/pci_def.h>
-#define _SA_DEV(slot)		pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
 #define _PCH_DEV(slot, func)	pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
 #endif
 
 /* System Agent Devices */
 
 #define SA_DEV_SLOT_ROOT	0x00
-#define  SA_DEVFN_ROOT		_SA_DEVFN(ROOT)
-#define  SA_DEV_ROOT		_SA_DEV(ROOT)
+#define  SA_DEVFN_ROOT		PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
+#define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
 
 #define SA_DEV_SLOT_IGD		0x02
-#define  SA_DEVFN_IGD		_SA_DEVFN(IGD)
-#define  SA_DEV_IGD		_SA_DEV(IGD)
+#define  SA_DEVFN_IGD		PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
+#define  SA_DEV_IGD		PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
 
 #define SA_DEV_SLOT_MINIHD	0x03
-#define  SA_DEVFN_MINIHD	_SA_DEVFN(MINIHD)
-#define  SA_DEV_MINIHD		_SA_DEV(MINIHD)
+#define  SA_DEVFN_MINIHD	PCI_DEVFN(SA_DEV_SLOT_MINIHD, 0)
+#define  SA_DEV_MINIHD		PCI_DEV(0, SA_DEV_SLOT_MINIHD, 0)
 
 /* PCH Devices */
 
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 9be4aebdd20a..b385d6b637bb 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -365,6 +365,7 @@ static void pch_cg_init(struct device *dev)
 {
 	u32 reg32;
 	u16 reg16;
+	struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 
 	/* DMI */
 	RCBA32_OR(0x2234, 0xf);
@@ -388,7 +389,7 @@ static void pch_cg_init(struct device *dev)
 	RCBA32_AND_OR(0x2614, ~0x64ff0000, 0x0a206500);
 
 	/* Check for 0:2.0@0x08 >= 0x0b */
-	if (pch_is_wpt() || pci_read_config8(SA_DEV_IGD, 0x8) >= 0x0b)
+	if (pch_is_wpt() || pci_read_config8(igd_dev, 0x8) >= 0x0b)
 		RCBA32_OR(0x2614, (1 << 26));
 
 	RCBA32_OR(0x900, 0x0000031f);
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 98c3c4cddd82..9ea73b205489 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -319,10 +319,11 @@ void smm_relocate(void)
 
 void smm_lock(void)
 {
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	/* LOCK the SMM memory window and enable normal SMM.
 	 * After running this function, only a full reset can
 	 * make the SMM registers writable again.
 	 */
 	printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+	pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
 }
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index c6444b15e8f5..b6b5608a2407 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -32,19 +32,22 @@
 
 u8 systemagent_revision(void)
 {
-	return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+	return pci_read_config8(sa_dev, PCI_REVISION_ID);
 }
 
 uintptr_t sa_get_tolud_base(void)
 {
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	/* Bit 0 is lock bit, not part of address */
-	return pci_read_config32(SA_DEV_ROOT, TOLUD) & ~1;
+	return pci_read_config32(sa_dev, TOLUD) & ~1;
 }
 
 uintptr_t sa_get_gsm_base(void)
 {
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	/* Bit 0 is lock bit, not part of address */
-	return pci_read_config32(SA_DEV_ROOT, BGSM) & ~1;
+	return pci_read_config32(sa_dev, BGSM) & ~1;
 }
 
 static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
@@ -291,6 +294,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 	uint64_t mc_values[NUM_MAP_ENTRIES];
 	unsigned long dpr_size = 0;
 	u32 dpr_reg;
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 
 	/* Read in the MAP registers and report their values. */
 	mc_read_map_entries(dev, &mc_values[0]);
@@ -302,7 +306,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 	 * the DPR register reports the TOP of the region, which is the same
 	 * as TSEG base.  The region size is reported in MiB in bits 11:4.
 	 */
-	dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR);
+	dpr_reg = pci_read_config32(sa_dev, DPR);
 	if (dpr_reg & DPR_EPM) {
 		dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16;
 		printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index 33814b033066..938b09a601a1 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -19,35 +19,32 @@
 
 #include <device/pci_def.h>
 
-#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot)		pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
 #define _PCH_DEV(slot, func)	pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
 #else
-#define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
 #endif
 
 /* System Agent Devices */
 
 #define SA_DEV_SLOT_ROOT	0x00
-#define  SA_DEVFN_ROOT		_SA_DEVFN(ROOT)
-#define  SA_DEV_ROOT		_SA_DEV(ROOT)
+#define  SA_DEVFN_ROOT		PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
+#define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
 
 #define SA_DEV_SLOT_IGD		0x02
-#define  SA_DEVFN_IGD		_SA_DEVFN(IGD)
-#define  SA_DEV_IGD		_SA_DEV(IGD)
+#define  SA_DEVFN_IGD		PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
+#define  SA_DEV_IGD		PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
 
 #define SA_DEV_SLOT_DSP		0x04
-#define  SA_DEVFN_DSP		_SA_DEVFN(DSP)
-#define  SA_DEV_DSP		_SA_DEV(DSP)
+#define  SA_DEVFN_DSP		PCI_DEVFN(SA_DEV_SLOT_DSP, 0)
+#define  SA_DEV_DSP		PCI_DEV(0, SA_DEV_SLOT_DSP, 0)
 
 #define SA_DEV_SLOT_IPU		0x05
-#define  SA_DEVFN_IPU		_SA_DEVFN(IPU)
-#define  SA_DEV_IPU		_SA_DEV(IPU)
+#define  SA_DEVFN_IPU		PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
+#define  SA_DEV_IPU		PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
 
 /* PCH Devices */
 #define PCH_DEV_SLOT_THERMAL	0x12
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 2576c9c1df3a..980702ffb6bc 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -301,11 +301,12 @@ void smm_relocate(void)
 
 void smm_lock(void)
 {
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	/*
 	 * LOCK the SMM memory window and enable normal SMM.
 	 * After running this function, only a full reset can
 	 * make the SMM registers writable again.
 	 */
 	printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+	pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
 }
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 7885ad7ccebd..26e1cb81aa7b 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -56,7 +56,7 @@ static uintptr_t graphics_get_bar(struct device *dev, unsigned long index)
 uintptr_t graphics_get_memory_base(void)
 {
 	uintptr_t memory_base;
-	struct device *dev = SA_DEV_IGD;
+	struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
 
 	if (is_graphics_disabled(dev))
 		return 0;
@@ -75,7 +75,7 @@ uintptr_t graphics_get_memory_base(void)
 static uintptr_t graphics_get_gtt_base(void)
 {
 	static uintptr_t gtt_base;
-	struct device *dev = SA_DEV_IGD;
+	struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
 
 	if (is_graphics_disabled(dev))
 		die("IGD is disabled!");
diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
index 27f9e35326a4..2e510d9b461f 100644
--- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h
+++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
@@ -21,16 +21,13 @@
 /* All these devices live on bus 0 with the associated device and function */
 
 
-#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0)
 #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func)
 
-#if ENV_RAMSTAGE
+#if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
 #include <device/pci_def.h>
-#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
 #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
 #else
-#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0)
 #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func)
 #endif
 
@@ -191,8 +188,8 @@
 
 /* TODO - New added */
 #define SA_DEV_SLOT_ROOT 0x00
-#define SA_DEVFN_ROOT _SA_DEVFN(ROOT)
-#define SA_DEV_ROOT _SA_DEV(ROOT)
+#define  SA_DEVFN_ROOT	PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
+#define  SA_DEV_ROOT	PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
 
 #define PCH_DEV_SLOT_LPC 0x1f
 #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h
index 0eddee279015..a9fd4ad46ad4 100644
--- a/src/soc/intel/icelake/include/soc/pci_devs.h
+++ b/src/soc/intel/icelake/include/soc/pci_devs.h
@@ -18,31 +18,28 @@
 
 #include <device/pci_def.h>
 
-#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot)		pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
 #define _PCH_DEV(slot, func)	pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
 #else
-#define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
 #endif
 
 /* System Agent Devices */
 
 #define SA_DEV_SLOT_ROOT	0x00
-#define  SA_DEVFN_ROOT		_SA_DEVFN(ROOT)
-#define  SA_DEV_ROOT		_SA_DEV(ROOT)
+#define  SA_DEVFN_ROOT		PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
+#define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
 
 #define SA_DEV_SLOT_IGD		0x02
-#define  SA_DEVFN_IGD		_SA_DEVFN(IGD)
-#define  SA_DEV_IGD		_SA_DEV(IGD)
+#define  SA_DEVFN_IGD		PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
+#define  SA_DEV_IGD		PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
 
 #define SA_DEV_SLOT_DSP		0x04
-#define  SA_DEVFN_DSP		_SA_DEVFN(DSP)
-#define  SA_DEV_DSP		_SA_DEV(DSP)
+#define  SA_DEVFN_DSP		PCI_DEVFN(SA_DEV_SLOT_DSP, 0)
+#define  SA_DEV_DSP		PCI_DEV(0, SA_DEV_SLOT_DSP, 0)
 
 /* PCH Devices */
 #define PCH_DEV_SLOT_THERMAL	0x12
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index 926ef63dbf89..63048eb91362 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -300,11 +300,12 @@ void smm_relocate(void)
 
 void smm_lock(void)
 {
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	/*
 	 * LOCK the SMM memory window and enable normal SMM.
 	 * After running this function, only a full reset can
 	 * make the SMM registers writable again.
 	 */
 	printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+	pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
 }
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 0669ced18cbe..7147876e9cb8 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -19,34 +19,26 @@
 
 #include <device/pci_def.h>
 
-#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot)		pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
 #define _PCH_DEV(slot, func)	pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
 #else
-#define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
 #endif
 
 /* System Agent Devices */
 
 #define SA_DEV_SLOT_ROOT	0x00
-#define  SA_DEVFN_ROOT		_SA_DEVFN(ROOT)
-#define  SA_DEV_ROOT		_SA_DEV(ROOT)
+#define  SA_DEVFN_ROOT		PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
+#define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
 
 #define SA_DEV_SLOT_PEG		0x01
-#define  SA_DEVFN_PEG(func)	PCI_DEVFN(SA_DEV_SLOT_PEG, func)
-#define  SA_DEV_PEG(func)	pcidev_path_on_root_debug(SA_DEVFN_PEG(func), __func__)
-#define  SA_DEV_PEG0		SA_DEV_PEG(0)
-#define  SA_DEV_PEG1		SA_DEV_PEG(1)
-#define  SA_DEV_PEG2		SA_DEV_PEG(2)
 
 #define SA_DEV_SLOT_IGD		0x02
-#define  SA_DEVFN_IGD		_SA_DEVFN(IGD)
-#define  SA_DEV_IGD		_SA_DEV(IGD)
+#define  SA_DEVFN_IGD		PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
+#define  SA_DEV_IGD		PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
 
 /* PCH Devices */
 
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index b15fa89292ff..bb86c6300d6b 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -223,7 +223,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
 	 * If PEG port is not defined in the device tree, it will be disabled
 	 * in FSP
 	 */
-	dev = SA_DEV_PEG0; /* PEG 0:1:0 */
+	dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */
 	if (!dev || !dev->enabled)
 		m_cfg->Peg0Enable = 0;
 	else if (dev->enabled) {
@@ -238,7 +238,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
 		m_t_cfg->Peg0Gen3EqPh3Method = 0;
 	}
 
-	dev = SA_DEV_PEG1; /* PEG 0:1:1 */
+	dev = pcidev_on_root(SA_DEV_SLOT_PEG, 1); /* PEG 0:1:1 */
 	if (!dev || !dev->enabled)
 		m_cfg->Peg1Enable = 0;
 	else if (dev->enabled) {
@@ -250,7 +250,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
 		m_t_cfg->Peg1Gen3EqPh3Method = 0;
 	}
 
-	dev = SA_DEV_PEG2; /* PEG 0:1:2 */
+	dev = pcidev_on_root(SA_DEV_SLOT_PEG, 2); /* PEG 0:1:2 */
 	if (!dev || !dev->enabled)
 		m_cfg->Peg2Enable = 0;
 	else if (dev->enabled) {
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 72861874c927..816e1a89633b 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -310,11 +310,12 @@ void smm_relocate(void)
 
 void smm_lock(void)
 {
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	/*
 	 * LOCK the SMM memory window and enable normal SMM.
 	 * After running this function, only a full reset can
 	 * make the SMM registers writable again.
 	 */
 	printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+	pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
 }
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index ea5526264b0c..410265f68e65 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -29,7 +29,7 @@
 
 bool soc_is_vtd_capable(void)
 {
-	struct device *const root_dev = SA_DEV_ROOT;
+	struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	return root_dev &&
 		!(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE);
 }
@@ -42,7 +42,8 @@ bool soc_is_vtd_capable(void)
  */
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 {
-	struct device *const igd_dev = SA_DEV_IGD;
+	struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
+
 	static const struct sa_mmio_descriptor soc_fixed_resources[] = {
 		{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
 				"PCIEXBAR" },
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 905154e8ac27..c83e18dd1da6 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -174,17 +174,19 @@ static uint16_t get_dev_id(struct device *dev)
 
 static int get_kbl_sku(void)
 {
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	static int sku = -1;
 	uint16_t id;
 
 	if (sku != -1)
 		return sku;
 
-	id = get_dev_id(SA_DEV_ROOT);
+	id = get_dev_id(sa_dev);
 	if (id == PCI_DEVICE_ID_INTEL_KBL_U_R)
 		sku = KBL_R_SKU;
 	else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y) {
-		id = get_dev_id(SA_DEV_IGD);
+		struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
+		id = get_dev_id(igd_dev);
 		if (id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX)
 			sku = AML_Y_SKU;
 		else