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| author | Kane Chen <kane.chen@intel.com> | 2015-02-12 16:08:42 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 20:33:04 +0200 |
| commit | bae8608435a1e7ff856f620a77666fed2a6c10fa (patch) | |
| tree | 1f18bbc4e7c95499c1457ffeeb9d920f4d78810c /src/soc/intel | |
| parent | 555f711cd2712a1c526dc3b64a1c193dc13ccca7 (diff) | |
| download | coreboot-bae8608435a1e7ff856f620a77666fed2a6c10fa.tar.gz coreboot-bae8608435a1e7ff856f620a77666fed2a6c10fa.tar.bz2 coreboot-bae8608435a1e7ff856f620a77666fed2a6c10fa.zip | |
baytrail: correct NC pin to GPO pin according to BYT platform design guide
According to BYT platform design guide chap 14.2.2, the NC GPIOs
need to be configured to GPO.
BRANCH=none
BUG=none
TEST=Test on rambi, boot to OS, and make sure NC pins config to GPO
Change-Id: Ida5ea89ee66e39b4fddea242dc918b314756d94f
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 998493566f5cf7abd9375583e12fe631b226e591
Original-Change-Id: Ieaf346d1c7bf3ecb47a71a6ee4afaa805235cc37
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/249060
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9509
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/gpio.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 413ade2d86f7..f312cdc65fd2 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -322,7 +322,7 @@ #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU #define GPIO_INPUT_PU GPIO_INPUT_PU_20K #define GPIO_INPUT_PD GPIO_INPUT_PD_20K -#define GPIO_NC GPIO_INPUT_PU_20K +#define GPIO_NC GPIO_OUT_HIGH #define GPIO_DEFAULT GPIO_FUNC0 /* 16 DirectIRQs per supported bank */ |