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| author | Subrata Banik <subrata.banik@intel.com> | 2021-09-21 21:00:16 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-09-30 07:08:03 +0000 |
| commit | bee4bb5f0d157bc360aaf5d70d7ac2b91b18af48 (patch) | |
| tree | cda73ae240bef70ce992c619caccbae909dc1417 /src/soc/intel | |
| parent | a834a6eede3065b954f8bebcc77bd2df557b4a18 (diff) | |
| download | coreboot-bee4bb5f0d157bc360aaf5d70d7ac2b91b18af48.tar.gz coreboot-bee4bb5f0d157bc360aaf5d70d7ac2b91b18af48.tar.bz2 coreboot-bee4bb5f0d157bc360aaf5d70d7ac2b91b18af48.zip | |
soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM
Pushing EOP msg post FSP notify helps to save ~30ms+ boot time across
various warm reboots.
This patch ensures late sending EOP msg when function disabling of CSE
is no longer a requirement.
BUG=b:200644229
TEST=Able to save ~30ms+ of boot time
Without this code change EOP sending timestamp as below:
943:after sending EOP to ME 1,248,328(61,954))
With this code change EOP sending timestamp as below:
943:after sending EOP to ME 1,231,660 (2,754)
Change-Id: I2b78a1c07803aacfb34dce9e94b2a05a2491aabc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_eop.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 0da49b2b495c..c9bbfff58687 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -185,10 +185,15 @@ static void set_cse_end_of_post(void *unused) /* * Ideally, to give coreboot maximum flexibility, sending EOP would be done as - * late possible, just before loading the payload, which would be BS_ON_EXIT - * here, but the platforms this is currently supported for all select - * HECI_DISABLE_USING_SMM, which runs in BS_ON_EXIT. Because sending EOP - * requires HECI to be up, and it is not trivial to control the order in which - * these callbacks are issued, it is called on BS_ON_ENTRY. + * late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must + * be performed before the HECI bus is disabled, so these boards use + * BS_PAYLOAD_LOAD, which happens before the HECI_DISABLE_USING_SMM Kconfig takes + * effect (EOP is sent using the HECI bus). + * Otherwise, EOP can be pushed a little later, and can be performed in + * BS_PAYLOAD_BOOT instead. */ +#if !CONFIG(HECI_DISABLE_USING_SMM) +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_cse_end_of_post, NULL); +#else BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, set_cse_end_of_post, NULL); +#endif |