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| author | Sean Rhodes <sean@starlabs.systems> | 2022-05-21 10:45:02 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-30 14:08:50 +0000 |
| commit | e68175cad3fe215b4ada859784ec4f9c7064b62d (patch) | |
| tree | c95bb5e8fbc09a965d1ebbdfa599bf072d2613b1 /src/soc/intel | |
| parent | 75a423ed7b3a9d04f02bdc77498b1681e0461ac8 (diff) | |
| download | coreboot-e68175cad3fe215b4ada859784ec4f9c7064b62d.tar.gz coreboot-e68175cad3fe215b4ada859784ec4f9c7064b62d.tar.bz2 coreboot-e68175cad3fe215b4ada859784ec4f9c7064b62d.zip | |
soc/alderlake: Enable all bits for IO decode / enable register
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I86423c45ca33a79d3d8cf8e4ca4737da94a4aa4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/pch.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 893956b25945..712c128d07e4 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -17,6 +17,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <soc/bootblock.h> +#include <soc/soc_chip.h> #include <soc/espi.h> #include <soc/iomap.h> #include <soc/p2sb.h> @@ -97,8 +98,11 @@ static void soc_config_acpibase(void) void pch_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F | - LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + uint16_t io_enables = LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | + LPC_IOE_LPT_EN | LPC_IOE_FDD_EN | + LPC_IOE_LGE_200 | LPC_IOE_HGE_208 | + LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | + LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F; /* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO)) |