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| author | Divya Chellap <divya.chellappa@intel.com> | 2017-12-19 20:16:50 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-22 16:43:17 +0000 |
| commit | e7fb7ce06577d88a193c8553b2d94c12eb256c58 (patch) | |
| tree | e14ad6b678a80c6112dfc0f67e84ba9c1094e8ca /src/soc/intel | |
| parent | 361d197d7789f1a974eff05c7a6d7debc0929646 (diff) | |
| download | coreboot-e7fb7ce06577d88a193c8553b2d94c12eb256c58.tar.gz coreboot-e7fb7ce06577d88a193c8553b2d94c12eb256c58.tar.bz2 coreboot-e7fb7ce06577d88a193c8553b2d94c12eb256c58.zip | |
soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.
BUG=b:70252901
BRANCH=None
TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka
Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 13 |
2 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 813974909a06..00088b9aad64 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -200,6 +200,11 @@ struct soc_intel_skylake_config { u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS]; /* + * Clk source number for Root Port + */ + u8 PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS]; + + /* * Enable/Disable AER (Advanced Error Reporting) for Root Port * 0: Disable AER * 1: Enable AER diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 96c3b608afec..24a239e3b5c8 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -166,6 +166,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); + /* + * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for + * all the enabled PCIe root ports, invalid(0x1F) is set for + * disabled PCIe root ports. + */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + if (config->PcieRpClkReqSupport[i]) + params->PcieRpClkSrcNumber[i] = + config->PcieRpClkSrcNumber[i]; + else + params->PcieRpClkSrcNumber[i] = 0x1F; + } + /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); |