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| author | Jitao Shi <jitao.shi@mediatek.com> | 2021-02-01 13:21:45 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-03-27 10:03:41 +0000 |
| commit | 927fa6d04c0c4f61140bd680c1bd8e06191ea407 (patch) | |
| tree | b0bbdae81b673e5d7b927d5c10018356e684726e /src/soc/mediatek/common/include/soc/dsi_common.h | |
| parent | 7de5677643294ae021f7012e45dce416639224b2 (diff) | |
| download | coreboot-927fa6d04c0c4f61140bd680c1bd8e06191ea407.tar.gz coreboot-927fa6d04c0c4f61140bd680c1bd8e06191ea407.tar.bz2 coreboot-927fa6d04c0c4f61140bd680c1bd8e06191ea407.zip | |
soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_END
ANX7625 requires the line packets to end at the same time.
Otherwise, the display will be shifted.
BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Jacuzzi
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I5949de1a9a1947fa188233787166a478b1de68b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/common/include/soc/dsi_common.h')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/dsi_common.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index aebe62aa367d..489a5918908b 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -39,7 +39,9 @@ enum { /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), /* transmit data in low power */ - MIPI_DSI_MODE_LPM = BIT(11) + MIPI_DSI_MODE_LPM = BIT(11), + /* dsi per line's data end same time on all lanes */ + MIPI_DSI_MODE_LINE_END = BIT(12), }; struct dsi_regs { |