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| author | Tristan Shieh <tristan.shieh@mediatek.com> | 2018-08-09 15:14:15 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-13 12:22:52 +0000 |
| commit | 1efe2578c00e18cfc409f2ecfd95118f95a0d69c (patch) | |
| tree | 1f995ea7195900ea601a2eab78895cbfce85d5b5 /src/soc/mediatek/common/mmu_operations.c | |
| parent | 4cb8ac234bc92e6b126c869948593409702d9607 (diff) | |
| download | coreboot-1efe2578c00e18cfc409f2ecfd95118f95a0d69c.tar.gz coreboot-1efe2578c00e18cfc409f2ecfd95118f95a0d69c.tar.bz2 coreboot-1efe2578c00e18cfc409f2ecfd95118f95a0d69c.zip | |
mediatek: Map SRAM as secure and cached memory
This patch changes the mapping of SRAM from non-secure to secure.
Without this patch, mmu_config_range() can not work when MMU is
enabled. The new config is still in non-secure cache since TTB section
is allocated in SRAM which is mapped as non-secure.
BUG=b:80501386
TEST=Boots correctly on Kukui and Elm
Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/common/mmu_operations.c')
| -rw-r--r-- | src/soc/mediatek/common/mmu_operations.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index b9910845c10a..27a03e3317a5 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -25,17 +25,22 @@ void mtk_mmu_init(void) { mmu_init(); - /* Set 0x0 to the end of 2GB dram address as device memory */ - mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM); + /* + * Set 0x0 to 4GB address as device memory. We want to config IO_PHYS + * address to DEV_MEM, and map a proper range of dram for the memory + * test during calibration. + */ + mmu_config_range((void *)0, (uintptr_t)4U * GiB, DEV_MEM); /* SRAM is cached */ - mmu_config_range(_sram, _sram_size, CACHED_MEM); + mmu_config_range(_sram, _sram_size, SECURE_CACHED_MEM); /* L2C SRAM is cached */ - mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM); + mmu_config_range(_sram_l2c, _sram_l2c_size, SECURE_CACHED_MEM); /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ - mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); + mmu_config_range(_dma_coherent, _dma_coherent_size, + SECURE_UNCACHED_MEM); mmu_enable(); } @@ -43,7 +48,7 @@ void mtk_mmu_init(void) void mtk_mmu_after_dram(void) { /* Map DRAM as cached now that it's up and running */ - mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM); + mmu_config_range(_dram, (uintptr_t)sdram_size(), NONSECURE_CACHED_MEM); mtk_soc_after_dram(); } |