soc/mediatek: dsi: Refactor PHY timing calculation

The PHY timing should be calculated by data rate (Mbps). However for
8173 some values were hard-coded so we want to introduce a new
mtk_phy_timing structure and a weak function mtk_dsi_override_phy_timing
that allows per-SOC customization to apply PHY timings.

BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots

Change-Id: I1176ca06dda026029ff431aca7f9e21479eed670
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

1 files changed, 17 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c
index 2e4a4bd58a85..32f4f1ce1c80 100644
--- a/src/soc/mediatek/mt8173/dsi.c
+++ b/src/soc/mediatek/mt8173/dsi.c
@@ -107,6 +107,23 @@ void mtk_dsi_reset(void)
 	clrbits_le32(&dsi0->dsi_con_ctrl, 1);
 }
 
+void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)
+{
+	int lpx = 5;
+	timing->lpx = lpx;
+	timing->da_hs_prepare = 6;
+	timing->da_hs_zero = 10;
+	timing->da_hs_trail = 8;
+
+	timing->ta_go = 4 * lpx;
+	timing->ta_sure = 3 * lpx / 2;
+	timing->ta_get = 5 * lpx;
+	timing->da_hs_exit = 7;
+
+	timing->da_hs_sync = 0;
+	timing->clk_hs_exit = 2 * lpx;
+}
+
 void mtk_dsi_pin_drv_ctrl(void)
 {
 	struct stopwatch sw;