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| author | Yu-Ping Wu <yupingso@chromium.org> | 2019-10-29 16:20:35 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-31 10:31:58 +0000 |
| commit | 02d9071a0b4d0720dde569de9550c17d89bc100a (patch) | |
| tree | d378c80e9a7f115ef99f33f89876a7a80e3dab45 /src/soc/mediatek/mt8183/include/soc/dramc_param.h | |
| parent | 7d9d63b79f331d6a9c613bce03d6e09ef8745bbe (diff) | |
| download | coreboot-02d9071a0b4d0720dde569de9550c17d89bc100a.tar.gz coreboot-02d9071a0b4d0720dde569de9550c17d89bc100a.tar.bz2 coreboot-02d9071a0b4d0720dde569de9550c17d89bc100a.zip | |
soc/mediatek/mt8183: Disable DRAM DVFS in recovery mode
Currently full calibration with DVFS (which implies tripling memory
training time for multiple frequencies) will be run in recovery mode,
which takes up to 30 seconds with serial console enabled.
However, in recovery mode the system should be running only the recovery
programs with minimal services. DVFS should be not needed.
In order to improve stability and system boot time, we want to disable
DVFS training in recovery mode.
BRANCH=kukui
BUG=b:142358843
TEST=emerge-kukui coreboot
Change-Id: I4f1b1b020eba9bfce21655169bcb31b98d54b010
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36456
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/include/soc/dramc_param.h')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/dramc_param.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h index 564b43df9d02..1f4148bc8d08 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -23,7 +23,7 @@ enum { DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, - DRAMC_PARAM_HEADER_VERSION = 1, + DRAMC_PARAM_HEADER_VERSION = 2, }; enum DRAMC_PARAM_STATUS_CODES { @@ -43,6 +43,7 @@ enum DRAMC_PARAM_STATUS_CODES { /* Bit flags */ enum DRAMC_PARAM_CONFIG { DRAMC_CONFIG_EMCP = 0x0001, + DRAMC_CONFIG_DVFS = 0x0002, }; enum DRAMC_PARAM_FLAGS { |