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| author | Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> | 2020-12-04 17:00:56 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-15 11:29:17 +0000 |
| commit | 5ff588dbc10bbf69f140cebf3a584f1ed563b1c5 (patch) | |
| tree | fd72c40c3efe8160bb36f8c70ef14531c949de01 /src/soc/mediatek/mt8183/include/soc/emi.h | |
| parent | f296273692785da1bc88df8d28d955f8d79390e7 (diff) | |
| download | coreboot-5ff588dbc10bbf69f140cebf3a584f1ed563b1c5.tar.gz coreboot-5ff588dbc10bbf69f140cebf3a584f1ed563b1c5.tar.bz2 coreboot-5ff588dbc10bbf69f140cebf3a584f1ed563b1c5.zip | |
soc/mediatek/mt8183: Support byte mode and single rank DDR
1. Add emi setting to support byte mode and single rank ddr sample
2. Modify initial setting for DDR with different architecture
BUG=b:165768895
BRANCH=kukui
TEST=DDR boot up correctly on Kukui
Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: Id2845b2b60e2c447486ee25259dc6a05a0bb619b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8183/include/soc/emi.h')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/emi.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 6931d5bb8150..16f0b2e8f5e4 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -15,6 +15,7 @@ enum DRAMC_PARAM_SOURCE { struct sdram_params { u16 source; /* DRAMC_PARAM_SOURCE */ u16 frequency; + u32 rank_num; u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; |