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| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-06-01 16:30:27 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-09-25 01:33:11 +0000 |
| commit | 63ee16075e7e4dee90c0cb9b05caeb91f77bf1e5 (patch) | |
| tree | 31a9df5073b1248a6dece2d390e017da733e3a31 /src/soc/mediatek/mt8183/include/soc/emi.h | |
| parent | 92c1546c01795f8c8c079e7ea03c9cb36314e92a (diff) | |
| download | coreboot-63ee16075e7e4dee90c0cb9b05caeb91f77bf1e5.tar.gz coreboot-63ee16075e7e4dee90c0cb9b05caeb91f77bf1e5.tar.bz2 coreboot-63ee16075e7e4dee90c0cb9b05caeb91f77bf1e5.zip | |
soc/mediatek/mt8183: Enable CA perbit mechanism
LPDDR4x has 6 CA PINs, but for some 8GB LPDDR4X DDR, the left margin
of some CA PIN window is too small than others. Need to enable the CA
perbit mechanism to avoid those risks.
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41965
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/include/soc/emi.h')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/emi.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index cf794dee8951..6931d5bb8150 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -27,6 +27,7 @@ struct sdram_params { u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]; u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_ca_perbit_delay[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]; /* Gating */ u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; |