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| author | Huayang Duan <huayang.duan@mediatek.com> | 2019-08-30 18:01:19 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-09 22:22:14 +0000 |
| commit | 846be446d3099544c2d1029ca2b7884c1641441d (patch) | |
| tree | b93fde6d1f578d25b5a9e603197e509a1d658fed /src/soc/mediatek/mt8183/include/soc/memlayout.ld | |
| parent | 732e215dd82f606402c27a409c209f87687512fc (diff) | |
| download | coreboot-846be446d3099544c2d1029ca2b7884c1641441d.tar.gz coreboot-846be446d3099544c2d1029ca2b7884c1641441d.tar.bz2 coreboot-846be446d3099544c2d1029ca2b7884c1641441d.zip | |
soc/mediatek/mt8183: Use cached calibration result for faster bootup
Load calibration params from flash. If the format of the params is
correct, use these calibration params for fast calibration to reduce the
bootup time.
Bootup time of DRAM partial calibration:
- 1,349,385 usecs with low frequency
- 924,698 usecs with middle frequency
- 1,270,089 usecs with high frequency
3,544,172 usecs in total.
Bootup time of DRAM fast calibration:
- 216,663 usecs with low frequency
- 328,220 usecs with middle frequency
- 322,612 usecs with high frequency
867,495 usecs in total.
BUG=b:139099592
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35164
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/include/soc/memlayout.ld')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/memlayout.ld | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 73c880afbf8e..82e404f790c9 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -24,6 +24,8 @@ */ #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 4) SECTIONS { @@ -42,6 +44,7 @@ SECTIONS SRAM_L2C_START(0x00200000) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) BOOTBLOCK(0x00230000, 64K) + DRAM_INIT_CODE(0x00240000, 256K) SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) |