soc/mediatek: dsi: Increase pcw precision

When configuring MIPI DSI Tx, the value of pcw was calculated from data
rate in MHz, leading to loss of precision. This patch changes to use
data rate in Hz for the calculation so that the resulting value should
be consistent with the one in kernel (CL:1786327).

In addition, change the type of data rate to u32, and calculation of
data rate from pixel clock is changed to use DIV_ROUND_UP for
consistency with kernel (CL:1761843).

Also remove unused variable txdiv.

BRANCH=kukui
BUG=b:149051882
TEST=emerge-jacuzzi coreboot
TEST=No scrolling issue on Juniper AUO and InnoLux panels

Change-Id: I23220d446833b956431006027bbc8cb20fc696a5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38827
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 10 insertions, 14 deletions

diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c
index 7f5ac0a747a8..3710fc652cb4 100644
--- a/src/soc/mediatek/mt8183/dsi.c
+++ b/src/soc/mediatek/mt8183/dsi.c
@@ -19,32 +19,28 @@
 #include <soc/dsi.h>
 #include <soc/pll.h>
 
-void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
+void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
 {
-	unsigned int txdiv, txdiv0, txdiv1;
+	unsigned int txdiv0, txdiv1;
 	u64 pcw;
 
-	if (data_rate >= 2000) {
-		txdiv = 1;
+	if (data_rate >= 2000 * MHz) {
 		txdiv0 = 0;
 		txdiv1 = 0;
-	} else if (data_rate >= 1000) {
-		txdiv = 2;
+	} else if (data_rate >= 1000 * MHz) {
 		txdiv0 = 1;
 		txdiv1 = 0;
-	} else if (data_rate >= 500) {
-		txdiv = 4;
+	} else if (data_rate >= 500 * MHz) {
 		txdiv0 = 2;
 		txdiv1 = 0;
-	} else if (data_rate > 250) {
-		/* Be aware that 250 is a special case that must use txdiv=4. */
-		txdiv = 8;
+	} else if (data_rate > 250 * MHz) {
+		/* (data_rate == 250MHz) is a special case that should go to the
+		   else-block below (txdiv0 = 4) */
 		txdiv0 = 3;
 		txdiv1 = 0;
 	} else {
 		/* MIN = 125 */
-		assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ);
-		txdiv = 16;
+		assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
 		txdiv0 = 4;
 		txdiv1 = 0;
 	}
@@ -56,7 +52,7 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
 
 	pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1);
 	pcw <<= 24;
-	pcw /= CLK26M_HZ / MHz;
+	pcw /= CLK26M_HZ;
 
 	write32(&mipi_tx->pll_con0, pcw);
 	clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);