soc/mediatek/mt8186: Add support for PMIC MT6315

On MT8186T, the big cores are powered on by MT6315 via PMIF. This
patch adds the following changes.
- Add MT6315 settings.
- Configure PMIC PMIF for MT6315.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 142 insertions, 2 deletions

diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h
index 33a232740a33..5f0b10c5e03e 100644
--- a/src/soc/mediatek/mt8186/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h
@@ -29,10 +29,14 @@ enum {
 	EINT_BASE			= IO_PHYS + 0x0000B000,
 	APMIXED_BASE			= IO_PHYS + 0x0000C000,
 	PWRAP_BASE			= IO_PHYS + 0x0000D000,
+	/* Add PMICSPI_MST_BASE and PMIF_SPI_BASE to solve the build error */
+	PMICSPI_MST_BASE		= IO_PHYS + 0x0000D000,
+	PMIF_SPI_BASE			= IO_PHYS + 0x0000D000,
 	DEVAPC_AO_INFRA_PERI_BASE	= IO_PHYS + 0x0000E000,
 	DEVAPC_AO_MM_BASE		= IO_PHYS + 0x0000F000,
-	PMIF_BASE			= IO_PHYS + 0x00015000,
+	PMIF_SPMI_BASE			= IO_PHYS + 0x00015000,
 	SYSTIMER_BASE			= IO_PHYS + 0x00017000,
+	SPMI_MST_BASE			= IO_PHYS + 0x0001B000,
 	I2C0_DMA_BASE			= IO_PHYS + 0x00200100,
 	I2C1_DMA_BASE			= IO_PHYS + 0x00200200,
 	I2C2_DMA_BASE			= IO_PHYS + 0x00200300,
@@ -50,6 +54,7 @@ enum {
 	DRAMC_CHA_AO_BASE		= IO_PHYS + 0x00220000,
 	SSPM_SRAM_BASE			= IO_PHYS + 0x00400000,
 	SSPM_CFG_BASE			= IO_PHYS + 0x00440000,
+	SCP_CLK_BASE			= IO_PHYS + 0x005C4000,
 	AUDIODSP_BASE			= IO_PHYS + 0x00680000,
 	DEVAPC_AO_AUD_BASE		= IO_PHYS + 0x0069C000,
 	SFLASH_REG_BASE			= IO_PHYS + 0x01000000,
diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h
index bcd00da23c72..8df7f96b7fcd 100644
--- a/src/soc/mediatek/mt8186/include/soc/pll.h
+++ b/src/soc/mediatek/mt8186/include/soc/pll.h
@@ -16,7 +16,8 @@ struct mtk_topckgen_regs {
 	u32 clk_mode;
 	u32 clk_cfg_update;
 	u32 clk_cfg_update1;
-	u32 reserved1[13];
+	u32 clk_cfg_update2;
+	u32 reserved1[12];
 	u32 clk_cfg_0;
 	u32 clk_cfg_0_set;
 	u32 clk_cfg_0_clr;
@@ -117,6 +118,7 @@ struct mtk_topckgen_regs {
 check_member(mtk_topckgen_regs, clk_mode, 0x0);
 check_member(mtk_topckgen_regs, clk_cfg_update, 0x4);
 check_member(mtk_topckgen_regs, clk_cfg_update1, 0x8);
+check_member(mtk_topckgen_regs, clk_cfg_update2, 0xc);
 check_member(mtk_topckgen_regs, clk_cfg_0, 0x40);
 check_member(mtk_topckgen_regs, clk_cfg_0_set, 0x44);
 check_member(mtk_topckgen_regs, clk_cfg_0_clr, 0x48);
diff --git a/src/soc/mediatek/mt8186/include/soc/pmif.h b/src/soc/mediatek/mt8186/include/soc/pmif.h
index 0e1e1a276d25..2eecb26c0873 100644
--- a/src/soc/mediatek/mt8186/include/soc/pmif.h
+++ b/src/soc/mediatek/mt8186/include/soc/pmif.h
@@ -8,9 +8,142 @@
 #ifndef __SOC_MEDIATEK_MT8186_PMIF_H__
 #define __SOC_MEDIATEK_MT8186_PMIF_H__
 
+#include <device/mmio.h>
 #include <soc/addressmap.h>
+#include <soc/pmif_common.h>
 #include <types.h>
 
+/* indicate which number SW channel start, by project */
+#define PMIF_SPMI_SW_CHAN	0xFFFFFFFF
+#define PMIF_SPMI_INF		0xFFFFFFFF
+
+struct mtk_pmif_regs {
+	u32 init_done;
+	u32 reserved1[5];
+	u32 inf_busy_sta;
+	u32 other_busy_sta_0;
+	u32 other_busy_sta_1;
+	u32 inf_en;
+	u32 other_inf_en;
+	u32 inf_cmd_per_0;
+	u32 inf_cmd_per_1;
+	u32 inf_cmd_per_2;
+	u32 inf_cmd_per_3;
+	u32 inf_max_bytecnt_per_0;
+	u32 inf_max_bytecnt_per_1;
+	u32 inf_max_bytecnt_per_2;
+	u32 inf_max_bytecnt_per_3;
+	u32 staupd_ctrl;
+	u32 reserved2[48];
+	u32 int_gps_auxadc_cmd_addr;
+	u32 int_gps_auxadc_cmd;
+	u32 int_gps_auxadc_rdata_addr;
+	u32 reserved3[13];
+	u32 arb_en;
+	u32 reserved4[34];
+	u32 lat_cnter_ctrl;
+	u32 lat_cnter_en;
+	u32 lat_limit_loading;
+	u32 lat_limit_0;
+	u32 lat_limit_1;
+	u32 lat_limit_2;
+	u32 lat_limit_3;
+	u32 lat_limit_4;
+	u32 lat_limit_5;
+	u32 lat_limit_6;
+	u32 lat_limit_7;
+	u32 lat_limit_8;
+	u32 lat_limit_9;
+	u32 reserved5[99];
+	u32 crc_ctrl;
+	u32 crc_sta;
+	u32 sig_mode;
+	u32 pmic_sig_addr;
+	u32 pmic_sig_val;
+	u32 reserved6[2];
+	u32 cmdissue_en;
+	u32 reserved7[10];
+	u32 timer_ctrl;
+	u32 timer_sta;
+	u32 sleep_protection_ctrl;
+	u32 reserved8[6];
+	u32 spi_mode_ctrl;
+	u32 reserved9[2];
+	u32 pmic_eint_sta_addr;
+	u32 reserved10[2];
+	u32 irq_event_en_0;
+	u32 irq_flag_raw_0;
+	u32 irq_flag_0;
+	u32 irq_clr_0;
+	u32 reserved11[244];
+	u32 swinf_0_acc;
+	u32 swinf_0_wdata_31_0;
+	u32 swinf_0_wdata_63_32;
+	u32 reserved12[2];
+	u32 swinf_0_rdata_31_0;
+	u32 swinf_0_rdata_63_32;
+	u32 reserved13[2];
+	u32 swinf_0_vld_clr;
+	u32 swinf_0_sta;
+	u32 reserved14[5];
+	u32 swinf_1_acc;
+	u32 swinf_1_wdata_31_0;
+	u32 swinf_1_wdata_63_32;
+	u32 reserved15[2];
+	u32 swinf_1_rdata_31_0;
+	u32 swinf_1_rdata_63_32;
+	u32 reserved16[2];
+	u32 swinf_1_vld_clr;
+	u32 swinf_1_sta;
+	u32 reserved17[5];
+	u32 swinf_2_acc;
+	u32 swinf_2_wdata_31_0;
+	u32 swinf_2_wdata_63_32;
+	u32 reserved18[2];
+	u32 swinf_2_rdata_31_0;
+	u32 swinf_2_rdata_63_32;
+	u32 reserved19[2];
+	u32 swinf_2_vld_clr;
+	u32 swinf_2_sta;
+	u32 reserved20[5];
+	u32 swinf_3_acc;
+	u32 swinf_3_wdata_31_0;
+	u32 swinf_3_wdata_63_32;
+	u32 reserved21[2];
+	u32 swinf_3_rdata_31_0;
+	u32 swinf_3_rdata_63_32;
+	u32 reserved22[2];
+	u32 swinf_3_vld_clr;
+	u32 swinf_3_sta;
+	u32 reserved23[133];
+};
+check_member(mtk_pmif_regs, inf_busy_sta, 0x18);
+check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110);
+check_member(mtk_pmif_regs, arb_en, 0x0150);
+check_member(mtk_pmif_regs, lat_cnter_en, 0x1E0);
+check_member(mtk_pmif_regs, crc_ctrl, 0x39C);
+check_member(mtk_pmif_regs, cmdissue_en, 0x3B8);
+check_member(mtk_pmif_regs, timer_ctrl, 0x3E4);
+check_member(mtk_pmif_regs, spi_mode_ctrl, 0x408);
+check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x414);
+check_member(mtk_pmif_regs, irq_event_en_0, 0x420);
+check_member(mtk_pmif_regs, swinf_0_acc, 0x800);
+
+#define PMIF_SPMI_AP_CHAN	(PMIF_SPMI_BASE + 0x880)
+#define PMIF_SPI_AP_CHAN	(PMIF_SPI_BASE + 0xC20)
+
+enum {
+	FREQ_250MHZ = 250,
+};
+
+struct mtk_scp_clk_regs {
+	u32 reserved0;
+	u32 scp_clk_en;
+};
+check_member(mtk_scp_clk_regs, scp_clk_en, 0x4);
+
+#define mtk_scp_clk ((struct mtk_scp_clk_regs *)SCP_CLK_BASE)
+
 void pmif_spmi_set_lp_mode(void);
 
 #endif /*__SOC_MEDIATEK_MT8186_PMIF_H__*/