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| author | Housong Zhang <housong.zhang@mediatek.corp-partner.google.com> | 2021-11-01 11:00:09 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-11-17 10:30:06 +0000 |
| commit | 7c14ff0261951801bb7ff2aff8cfa25ca34b43ab (patch) | |
| tree | 4ea2aaac7d8397e2d38df54f87a5e8c468e07c2c /src/soc/mediatek/mt8186/include/soc | |
| parent | 9d321588d04843621af4cddff411ddcee88fe682 (diff) | |
| download | coreboot-7c14ff0261951801bb7ff2aff8cfa25ca34b43ab.tar.gz coreboot-7c14ff0261951801bb7ff2aff8cfa25ca34b43ab.tar.bz2 coreboot-7c14ff0261951801bb7ff2aff8cfa25ca34b43ab.zip | |
soc/mediatek/mt8186: Add I2C driver support
Add I2C controller drivers.
TEST=build pass
BUG=b:202871018
Signed-off-by: Housong Zhang <housong.zhang@mediatek.corp-partner.google.com>
Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8186/include/soc')
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/i2c.h | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/include/soc/i2c.h b/src/soc/mediatek/mt8186/include/soc/i2c.h new file mode 100644 index 000000000000..4024e7de6bd0 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/i2c.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.10 + */ + +#ifndef SOC_MEDIATEK_MT8186_I2C_H +#define SOC_MEDIATEK_MT8186_I2C_H + +#include <soc/i2c_common.h> +#include <soc/pll.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +/* I2C ID Number*/ +enum { + I2C0, + I2C1, + I2C2, + I2C3, + I2C4, + I2C5, + I2C6, + I2C7, + I2C8, + I2C9, +}; + +#define I2C_BUS_NUMBER 10 +#define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIV2PLL_HZ / 20) + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus, uint32_t speed); + +#endif /* SOC_MEDIATEK_MT8186_I2C_H */ |