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| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-12-06 10:20:42 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-12-08 11:32:14 +0000 |
| commit | eb102ccbd6a41d55478a8b9a95ef1f093ecaf82a (patch) | |
| tree | b30de10ab73f6f5752429863695f2d8faca02409 /src/soc/mediatek/mt8186/include/soc | |
| parent | d22e921178bcbdf1c72a19f95a1067f9074aaf58 (diff) | |
| download | coreboot-eb102ccbd6a41d55478a8b9a95ef1f093ecaf82a.tar.gz coreboot-eb102ccbd6a41d55478a8b9a95ef1f093ecaf82a.tar.bz2 coreboot-eb102ccbd6a41d55478a8b9a95ef1f093ecaf82a.zip | |
soc/mediatek/mt8186: Correct SPI_HZ for PLL
The SPI speed is 218.4MHz, so correct the value of SPI_HZ.
BUG=b:202871018
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I6e8ba10a851e1507405cdd41939a176462734487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8186/include/soc')
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/pll.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h index ce980774e255..c2dace32201e 100644 --- a/src/soc/mediatek/mt8186/include/soc/pll.h +++ b/src/soc/mediatek/mt8186/include/soc/pll.h @@ -492,12 +492,12 @@ enum { /* top_div rate */ enum { CLK26M_HZ = 26 * MHz, - UNIVPLL_D6_D2_HZ = UNIV2PLL_HZ / 2 / 6 / 2, + MAINPLL_D5_HZ = MAINPLL_HZ / 5, }; /* top_mux rate */ enum { - SPI_HZ = UNIVPLL_D6_D2_HZ, + SPI_HZ = MAINPLL_D5_HZ, UART_HZ = CLK26M_HZ, }; |