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| author | kewei.xu <kewei.xu@mediatek.corp-partner.google.com> | 2022-06-28 17:33:04 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-12 14:40:14 +0000 |
| commit | 2680eec0cd2b300c4738091555fa98e87f0af052 (patch) | |
| tree | 25d76c4bf97e75a1c74e7810b3f7edd7caea5d78 /src/soc/mediatek/mt8188/include | |
| parent | 132b6d20e835c229456f94d89ad68152ab46b499 (diff) | |
| download | coreboot-2680eec0cd2b300c4738091555fa98e87f0af052.tar.gz coreboot-2680eec0cd2b300c4738091555fa98e87f0af052.tar.bz2 coreboot-2680eec0cd2b300c4738091555fa98e87f0af052.zip | |
soc/mediatek/mt8188: Add I2C driver support
Add I2C controller drivers.
TEST=build pass
BUG=b:233720142
Signed-off-by: kewei.xu <kewei.xu@mediatek.corp-partner.google.com>
Change-Id: I7d19df3571e5588c7b20d9c7f26fa177b2221851
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8188/include')
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/i2c.h | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8188/include/soc/i2c.h b/src/soc/mediatek/mt8188/include/soc/i2c.h new file mode 100644 index 000000000000..1e46f29ef7c0 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/i2c.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8188 Functional Specification + * Chapter number: 5.11 + */ + +#ifndef SOC_MEDIATEK_MT8188_I2C_H +#define SOC_MEDIATEK_MT8188_I2C_H + +#include <soc/i2c_common.h> +#include <soc/pll.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t reserved0[1]; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved1[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved2[16]; + uint32_t slave_addr; + uint32_t reserved3[19]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved4[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved5[897]; + uint32_t sec_control; + uint32_t reserved6[31]; + uint32_t channel_lock; + uint32_t channel_sec; + uint32_t hw_cg_en; + uint32_t reserved7[1]; + uint32_t dma_req; + uint32_t dma_nreq; +}; + +/* I2C ID Number*/ +enum { + I2C0, + I2C1, + I2C2, + I2C3, + I2C4, + I2C5, + I2C6, +}; + +#define I2C_BUS_NUMBER 7 +#define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (124800000) + +check_member(mt_i2c_regs, dma_nreq, 0xf94); + +void mtk_i2c_bus_init(uint8_t bus, uint32_t speed); + +#endif /* SOC_MEDIATEK_MT8188_I2C_H */ |