soc/mediatek/mt8188: devapc: Add SCP domain setting

Configure the SCP to operate within domain 8, allowing it to access
only the necessary registers. Any unauthorized access will be prevented
by the DAPC.

- Set SCP domain from domain 0 to domain 8.
- Lock register settings down to prevent unexpected modification.

BUG=b:270657858
TEST=scp bootup successful with dapc settings

Change-Id: I049486c997542d91bd468e0f4662eafbca4c17e0
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77883
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

3 files changed, 39 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c
index b30856f3e8ee..03e0dfd6f5ff 100644
--- a/src/soc/mediatek/mt8188/devapc.c
+++ b/src/soc/mediatek/mt8188/devapc.c
@@ -1628,6 +1628,15 @@ static void dump_infra2_ao(uintptr_t base)
 	       base, read32(getreg(base, DOM_REMAP_0_0)));
 }
 
+static void dump_scp_master(uintptr_t base)
+{
+	printk(BIOS_DEBUG, "[DEVAPC] SCP_DOM0:%#x SCP_DOM1:%#x SCP_DOM2:%#x Lock:%#x\n",
+	       read32(getreg(base, SCP_DOM0)),
+	       read32(getreg(base, SCP_DOM1)),
+	       read32(getreg(base, SCP_DOM2)),
+	       read32(getreg(base, ONETIME_LOCK)));
+}
+
 static void infra_init(uintptr_t base)
 {
 	void *reg;
@@ -1745,6 +1754,27 @@ static void infra2_master_init(uintptr_t base)
 			FOUR_BIT_DOM_REMAP_7, DOMAIN_15);
 }
 
+static void scp_master_init(uintptr_t base)
+{
+	SET32_BITFIELDS(getreg(base, SCP_DOM0),
+			FOUR_BIT_DOM_REMAP_0, DOMAIN_8,
+			FOUR_BIT_DOM_REMAP_2, DOMAIN_8,
+			FOUR_BIT_DOM_REMAP_4, DOMAIN_8,
+			FOUR_BIT_DOM_REMAP_6, DOMAIN_8);
+
+	SET32_BITFIELDS(getreg(base, SCP_DOM1),
+			FOUR_BIT_DOM_REMAP_0, DOMAIN_8,
+			FOUR_BIT_DOM_REMAP_2, DOMAIN_8,
+			FOUR_BIT_DOM_REMAP_4, DOMAIN_8,
+			FOUR_BIT_DOM_REMAP_6, DOMAIN_8);
+
+	SET32_BITFIELDS(getreg(base, SCP_DOM2),
+			FOUR_BIT_DOM_REMAP_0, DOMAIN_8);
+
+	/* Let SCP_DOM registers be read-only for security */
+	write32(getreg(base, ONETIME_LOCK), 0x5);
+}
+
 const struct devapc_init_ops devapc_init[] = {
 	{ DEVAPC_INFRA_AO_BASE, infra_init, dump_infra_ao_apc },
 	{ DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc },
@@ -1752,6 +1782,7 @@ const struct devapc_init_ops devapc_init[] = {
 	{ DEVAPC_PERI_PAR_AO_BASE, peri_par_init, dump_peri_par_ao_apc },
 	{ DEVAPC_FMEM_AO_BASE, fmem_master_init, dump_fmem_ao },
 	{ DEVAPC_INFRA2_AO_BASE, infra2_master_init, dump_infra2_ao },
+	{ SCP_CFG_BASE, scp_master_init, dump_scp_master },
 };
 
 const size_t devapc_init_cnt = ARRAY_SIZE(devapc_init);
diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h
index 01620b4508e7..53e52146ea76 100644
--- a/src/soc/mediatek/mt8188/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h
@@ -58,6 +58,7 @@ enum {
 	INFRA_TRACKER_BASE	= IO_PHYS + 0x00314000,
 	SSPM_SRAM_BASE          = IO_PHYS + 0x00400000,
 	SSPM_CFG_BASE		= IO_PHYS + 0x00440000,
+	SCP_CFG_BASE		= IO_PHYS + 0x00700000,
 	SCP_ADSP_CFG_BASE	= IO_PHYS + 0x00720000,
 	DPM_PM_SRAM_BASE	= IO_PHYS + 0x00900000,
 	DPM_DM_SRAM_BASE	= IO_PHYS + 0x00920000,
diff --git a/src/soc/mediatek/mt8188/include/soc/devapc.h b/src/soc/mediatek/mt8188/include/soc/devapc.h
index 177cd3c4a525..d71377c2b80c 100644
--- a/src/soc/mediatek/mt8188/include/soc/devapc.h
+++ b/src/soc/mediatek/mt8188/include/soc/devapc.h
@@ -19,6 +19,13 @@ enum devapc_ao_offset {
 	AO_APC_CON = 0x00F00,
 };
 
+enum scp_offset {
+	SCP_DOM0 = 0xA0900,
+	SCP_DOM1 = 0xA0904,
+	SCP_DOM2 = 0xA0908,
+	ONETIME_LOCK = 0xA5104,
+};
+
 /******************************************************************************
  * STRUCTURE DEFINITION
  ******************************************************************************/