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| author | Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com> | 2021-03-16 14:29:12 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-03-17 00:33:27 +0000 |
| commit | a94fea1ee444b8f1359729064cd72c963d36ad3f (patch) | |
| tree | 6d3b85ae5fb3cfa6c7c8aeead38183167fafbec3 /src/soc/mediatek/mt8192/devapc.c | |
| parent | 535846763825f9bc4531b9322b1b61f3973cd6f8 (diff) | |
| download | coreboot-a94fea1ee444b8f1359729064cd72c963d36ad3f.tar.gz coreboot-a94fea1ee444b8f1359729064cd72c963d36ad3f.tar.bz2 coreboot-a94fea1ee444b8f1359729064cd72c963d36ad3f.zip | |
vendorcode/mt8192: devapc: fix register offset for PCIe domain
Correct the wrong offset for setting PCIe domain.
Change-Id: I9de2bdf5a0a4fb5b34985b11976fd50b397e97ba
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51512
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/devapc.c')
| -rw-r--r-- | src/soc/mediatek/mt8192/devapc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c index 9e3692e6348d..542c05f63315 100644 --- a/src/soc/mediatek/mt8192/devapc.c +++ b/src/soc/mediatek/mt8192/devapc.c @@ -13,7 +13,7 @@ static void infra_master_init(uintptr_t base) SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, 1, CPU_EB_SEC, 1); /* Domain */ - SET32_BITFIELDS(getreg(base, MAS_SEC_0), PCIE_DOM, MAS_DOMAIN_1); + SET32_BITFIELDS(getreg(base, MAS_DOM_0), PCIE_DOM, MAS_DOMAIN_1); SET32_BITFIELDS(getreg(base, MAS_DOM_1), SCP_SSPM_DOM, MAS_DOMAIN_2, CPU_EB_DOM, MAS_DOMAIN_2); |