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| author | Yu-Ping Wu <yupingso@chromium.org> | 2021-03-23 12:23:45 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-03-24 05:43:05 +0000 |
| commit | 25ef410423df812f626b77b695f151b6f221fa2e (patch) | |
| tree | b8172d0a48af9d38d9f60ac325542369befbfd64 /src/soc/mediatek/mt8192/include | |
| parent | cbe266142efa5020f05230c9e59f73a8263f0670 (diff) | |
| download | coreboot-25ef410423df812f626b77b695f151b6f221fa2e.tar.gz coreboot-25ef410423df812f626b77b695f151b6f221fa2e.tar.bz2 coreboot-25ef410423df812f626b77b695f151b6f221fa2e.zip | |
soc/mediatek/mt8192: Enlarge ROMSTAGE to 272K
Enlarge ROMSTAGE from 256K to 272K for the upcoming change of MRC cache
(CB:51620). To have more compact space usage, reduce BOOTBLOCK size from
64K to 60K (only 44K needed), and move starting address of DRAM blob
(DRAM_INIT_CODE) to 0x210000 (64K-aligned).
BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots
BRANCH=asurada
Cq-Depend: chrome-internal:3704751
Change-Id: I7aaf9faf048e0adcb3a7d856d40891762c9a6604
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/memlayout.ld | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index e84383ba445c..150bfdde7884 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -40,13 +40,13 @@ SECTIONS SRAM_L2C_START(0x00200000) /* 4K reserved for BOOTROM until BOOTBLOCK is started */ - BOOTBLOCK(0x00201000, 64K) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00211000, 252K) + BOOTBLOCK(0x00201000, 60K) /* * The needed size can be obtained by: * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz */ - DRAM_INIT_CODE(0x00250000, 256K) + DRAM_INIT_CODE(0x00210000, 240K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0024c000, 272K) PRERAM_CBFS_CACHE(0x00290000, 48K) PRERAM_CBMEM_CONSOLE(0x0029c000, 400K) SRAM_L2C_END(0x00300000) |